Abstract
The cost of efficient fault-effect analysis on gate-level (GL) and register-transfer level models is increasing due to the rising complexity of safety-critical systems on chip (SoCs). Virtual prototypes (VPs) based on transaction-level models are employed to speed-up safety verification. However, VP structures correlate poorly to GL models. This leads to the injection of pseudo-faults into VPs and to the development of suboptimal safety mechanisms for the SoC. To mitigate these drawbacks, in this paper, we propose a safety-verification flow for VPs to maintain 100 % correlation to GL models and to ensure the injection of realistic faults into VPs. Our approach’s key aspects are: matching points across abstraction levels and selective abstraction of GL functionality using compiled-code simulation. Measurements show two orders of magnitude speed-up over RTL models and three orders of magnitude over GL models. Moreover, the speed-up increases with design size.
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Acknowledgement
This work is partially supported by the German Federal Ministry of Education and Research (BMBF) in the project EffektiV (contract no. 01IS13022).
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Tabacaru, BA., Chaari, M., Ecker, W., Kruse, T., Novello, C. (2016). Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed. In: Skavhaug, A., Guiochet, J., Schoitsch, E., Bitsch, F. (eds) Computer Safety, Reliability, and Security. SAFECOMP 2016. Lecture Notes in Computer Science(), vol 9923. Springer, Cham. https://doi.org/10.1007/978-3-319-45480-1_12
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