Abstract
General purpose networks-on-chip (GP-NoC) are expected to feature tens or even hundreds of computational elements with complex communications infrastructure binding them into a connected network to achieve memory synchronization. The experience accumulated over the years in network design suggests that the knowledge of the traffic nature is mandatory for successful design of a networking technology. In this paper, based on the Intel CPU family, we describe traffic estimation techniques for modern multi-core GP-CPUs, discuss the traffic modeling procedure and highlight the implications of the traffic structure for GP-NoC research. The most important observation is that the traffic at internal interfaces appears to be random for external observer and has clearly identifiable batch structure.
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Acknowledgement
The authors are grateful to Alexander Antonov from ITMO University and Vitaly Petrov from Tampere University of Technology for insightful comments that allowed to improve this paper.
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Moltchanov, D., Kluchev, A., Kustarev, P., Borunova, K., Platunov, A. (2016). Intra-CPU Traffic Estimation and Implications on Networks-on-Chip Research. In: Galinina, O., Balandin, S., Koucheryavy, Y. (eds) Internet of Things, Smart Spaces, and Next Generation Networks and Systems. ruSMART NEW2AN 2016 2016. Lecture Notes in Computer Science(), vol 9870. Springer, Cham. https://doi.org/10.1007/978-3-319-46301-8_38
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DOI: https://doi.org/10.1007/978-3-319-46301-8_38
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