Abstract
The adoption of a system-level simulation environment based on standard methodologies is a valuable solution to handle system complexity and achieve best design optimization. This work is focused on the implementation of such a platform for High Energy Physics (HEP) applications, i.e. for next generation pixel detector readout chips in the framework of the RD53 collaboration. The generic and re-usable environment is capable of verifying different designs in an automated fashion under a wide and flexible stimuli space; it can also be used at different stages of the design process, from initial architecture optimization to final design verification.
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Marconi, S., Conti, E., Placidi, P., Scorzoni, A., Christiansen, J., Hemperek, T. (2017). A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications. In: De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2016. Lecture Notes in Electrical Engineering, vol 409. Springer, Cham. https://doi.org/10.1007/978-3-319-47913-2_5
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DOI: https://doi.org/10.1007/978-3-319-47913-2_5
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