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Matching Multiplications in Bit-Vector Formulas

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Verification, Model Checking, and Abstract Interpretation (VMCAI 2017)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 10145))

Abstract

Bit-vector formulas arising from hardware verification problems often contain word-level arithmetic operations. Empirical evidence shows that state-of-the-art SMT solvers are not very efficient at reasoning about bit-vector formulas with multiplication. This is particularly true when multiplication operators are decomposed and represented in alternative ways in the formula. We present a pre-processing heuristic that identifies certain types of decomposed multipliers, and adds special assertions to the input formula that encode the equivalence of sub-terms and word-level multiplication terms. The pre-processed formulas are then solved using an SMT solver. Our experiments with three SMT solvers show that our heuristic allows several formulas to be solved quickly, while the same formulas time out without the pre-processing step.

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Notes

  1. 1.

    https://github.com/rahuljain1989/Bit-vector-multiplication-pattern.

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Authors and Affiliations

  1. Indian Institute of Technology Bombay, Mumbai, India

    Supratik Chakraborty

  2. Tata Institute of Fundamental Research, Mumbai, India

    Ashutosh Gupta & Rahul Jain

Authors
  1. Supratik Chakraborty
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  2. Ashutosh Gupta
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  3. Rahul Jain
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Correspondence to Rahul Jain .

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Editors and Affiliations

  1. IRIF, Université Paris Diderot, Paris, France

    Ahmed Bouajjani

  2. VERIMAG, CNRS & Université Grenoble Alpes, Grenoble, France

    David Monniaux

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Chakraborty, S., Gupta, A., Jain, R. (2017). Matching Multiplications in Bit-Vector Formulas. In: Bouajjani, A., Monniaux, D. (eds) Verification, Model Checking, and Abstract Interpretation. VMCAI 2017. Lecture Notes in Computer Science(), vol 10145. Springer, Cham. https://doi.org/10.1007/978-3-319-52234-0_8

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  • DOI: https://doi.org/10.1007/978-3-319-52234-0_8

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