The updated online version of this chapter can be found at http://dx.doi.org/10.1007/978-3-319-59936-6_6
You have full access to this open access chapter, Download conference paper PDF
Erratum to: Chapter “Designing Parity Preserving Reversible Circuits” in: I. Phillips and H. Rahaman (Eds.), Reversible Computation, LNCS 10301, DOI: 10.1007/978-3-319-59936-6_6
The 6th and 7th row of Table 2 (starting with 101 and 110 respectively) must have “0” in their last column instead of “1”.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing AG
About this paper
Cite this paper
Paul, G., Chattopadhyay, A., Chandak, C. (2017). Erratum to: Designing Parity Preserving Reversible Circuits. In: Phillips, I., Rahaman, H. (eds) Reversible Computation. RC 2017. Lecture Notes in Computer Science(), vol 10301. Springer, Cham. https://doi.org/10.1007/978-3-319-59936-6_20
Download citation
DOI: https://doi.org/10.1007/978-3-319-59936-6_20
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-59935-9
Online ISBN: 978-3-319-59936-6
eBook Packages: Computer ScienceComputer Science (R0)