UPF Based Power Aware Dynamic Simulation

Abstract

UPF based power aware (PA) verification adopts several power dissipation reduction techniques based on the target design implementation and UPF power specification or intent, as discussed in Chap. 2. These techniques introduce numerous and complex verification issues and challenges in the functional and structural aspects of the design. Such artifacts are completely nonexistent in a non-PA verification environment. For example, the power aware requirements may affect the design functionality in terms of power On-Off sequences, different modes of power operation, state or data preservation operations, data propagation, logic resolution, power state transitions, power state transition coverage, power state cross coverage, and more.