Abstract
This paper introduces a novel AES structure capable of improving the robustness against power analysis attacks while allowing for a very compact structure with a potentially negligible area and performance impact. The proposed design is based on a low entropy masking scheme, where half of the time the true value and half of the time the complemented value are used to mask the power consumption variation. The obtained experimental results suggest that the area overhead for the protection against power analysis is as low as 5% LUT increase with a performance degradation of about 10%. When compared with the state of the art supported on FPGAs, efficiency improvements above 6 times and a throughput improvement of at least two times higher are achieved.
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Notes
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We can notice that the strongest leakage for the unprotected implementation happens slightly later than for the protected one, but we do not have an explanation of this situation.
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Acknowledgements
This work was partially supported by national funds through Fundação para a Ciência e a Tecnologia (FCT) with reference UID/CEC/50021/2013 and upon work from COST Action IC1403 CRYPTACUS, supported by COST (European Cooperation in Science and Technology).
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Chaves, R., Chmielewski, Ł., Regazzoni, F., Batina, L. (2018). SCA-Resistance for AES: How Cheap Can We Go?. In: Joux, A., Nitaj, A., Rachidi, T. (eds) Progress in Cryptology – AFRICACRYPT 2018. AFRICACRYPT 2018. Lecture Notes in Computer Science(), vol 10831. Springer, Cham. https://doi.org/10.1007/978-3-319-89339-6_7
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