Abstract
This paper presents an approach, which is applicable to parallel testing, to the generation of test patterns using the partitioning technique based on the exhaustive testing scheme. The suggested method can discover faults faster than the exhaustive testing scheme. It also shows that testing can be performed in parallel using the functionally partitioned blocks, rather than in linear. In this paper, a functional level description as well as the Boolean differential is used to generate a test pattern that can be inserted into in parallel.
This work was supported by Kyungnam University Research Fund.
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References
Lala, P.K.: Fault Tolerant and fault testable hardware design. Prentice Hall International, New York (1985)
Seiberman, G.M., Spillinger, I.: Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation. IEEE Transactions on Computer 40(1) (January 1991)
Tomas, S.P., Shen, J.P.: A survey of: functional level testing and testability measures, Res. Rep. CMUCAD-83-18, CarnegiMellon Univ., Pittsburgh, PA (1983)
Rajski, J., Tyszer, J.: Recursive Pseudoexhaustive Test Pattern Generation. IEEE Transactions on Computer 42(12) (December 1993)
Das, A.K., Sanyal, A., Pal Chaudhuri, P.: On characterization of cellular automata with matrix algebra. Inform. Sci. 65, 251–277 (1992)
Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital Systems Testing and Testable Design. Computer Science Press, New York (1990)
McCluskey, E.J.: Verification testing - A pseudoexhaustive test technique. IEEE Trans. Comput. C-33, 541–546 (1984)
Sobelman, G.E., Chen, C.H.: An eficient approach to pseudoexhaustive test generation for BIST design. In: Proc. ICCD, pp. 576–579 (1989)
Anderson, T., Lee, P.: Fault-tolerance. Principle and Practice. Prentice-Hall International, New York (1981)
Sellers, F.F.: Analyzing errors with the Boolean difference. IEEE Trans. Comput., 676–683 (July 1968)
Pradahan, D.K.: Fault-Tolerant Computing. Prentice-Hall, Englewood Cliffs (1986)
Parker, K.P., McCluskey, E.J.: Probablistic Treatment of General Combinational Networks. IEEE Trans. Computers 24(6), 668–670 (1975)
Pradahan, D.K.: Fault-Tolerant Computer System Design. Prentice-Hall International, New York (1993)
Konijnenburg, M.H., Van De Goor, A.J., Van der Linden, J.T.: Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Ristrictors. In: 5th Asian Test Symposium (ATS 1996), November 1996, pp. 29–33 (1996)
Chang, D., Marek-Sadowska, M.: Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs. IEEE Transactions on Computers, 565–578 (June 1999)
Huang, D.J., Kahng, A.B.: When Clusters Meet Partitions: New Density-Based Methods for Circuit Decomposition. In: Proc. of EDTC, March 1995, pp. 60–64 (1995)
Wiklund, K.: A gate Level Fault Simulation Toolkit, Charmers University of Technonology, Gothenburg, Sweden, Tech. Report 00-17 (2001)
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Kim, W.W. (2004). Parallel Testing Method by Partitioning Circuit Based on the Exhaustive Test. In: Laganá, A., Gavrilova, M.L., Kumar, V., Mun, Y., Tan, C.J.K., Gervasi, O. (eds) Computational Science and Its Applications – ICCSA 2004. ICCSA 2004. Lecture Notes in Computer Science, vol 3044. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24709-8_28
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DOI: https://doi.org/10.1007/978-3-540-24709-8_28
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