Abstract
We present new designs of low complexity and low latency systolic arrays for multiplication in GF(2m) when there is an irreducible all one polynomial (AOP) of degree m. Our proposed bit parallel array has a reduced latency and hardware complexity compared with previously proposed designs. For a cryptographic purpose, we derive a linear systolic array using our algorithm and show that our design has a latency m/2+1 and a throughput rate 1/(m/2+1). Compared with other linear systolic arrays, we find that our design has at least 50 percent reduced hardware complexity and latency, and has twice higher throughput rate. Therefore our multiplier provides a fast and a hardware efficient architecture for multiplication of two elements in GF(2m) for large m.
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Kwon, S., Kim, C.H., Hong, C.P. (2004). A Linear Systolic Array for Multiplication in GF(2m) for High Speed Cryptographic Processors. In: Laganá, A., Gavrilova, M.L., Kumar, V., Mun, Y., Tan, C.J.K., Gervasi, O. (eds) Computational Science and Its Applications – ICCSA 2004. ICCSA 2004. Lecture Notes in Computer Science, vol 3046. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24768-5_12
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DOI: https://doi.org/10.1007/978-3-540-24768-5_12
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