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Secure Logic Synthesis

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Field Programmable Logic and Application (FPL 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3203))

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Abstract

This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm can now be implemented with a mere doubling of the slice utilization when compared with a normal non-secure single ended implementation.

This work was supported in part by NSF grant CCR-0098361.

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References

  1. Wollinger, T., Paar, C.: How Secure Are FPGAs in Cryptographic Applications? In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 91–100. Springer, Heidelberg (2003)

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  2. Örs, B., Oswald, E., Preneel, B.: Power-Analysis Attacks on an FPGA – First Experimental Results. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 35–50. Springer, Heidelberg (2003)

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  3. Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: Proc. of DATE 2004, February 2004, pp. 246–251 (2004)

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  4. Shang, L., Kaviani, A.S., Bathala, K.: Dynamic Power Consumption in Virtex-II FPGA Family. In: Proc. of FPGA 2002, February 2002, pp. 157–164 (2002)

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  5. Tiri, K., Verbauwhede, I.: Synthesis of Secure FPGA Implementations. UCLA Internal report, available as report 2004/068 from the IACR Cryptology ePrint Archive (February 2004)

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Author information

Authors and Affiliations

  1. UC Los Angeles,  

    Kris Tiri & Ingrid Verbauwhede

  2. K.U.Leuven,  

    Ingrid Verbauwhede

Authors
  1. Kris Tiri
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  2. Ingrid Verbauwhede
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Editor information

Editors and Affiliations

  1. ITIV - Universitaet Karlsruhe (TH),  

    Jürgen Becker

  2. University of Paderborn,  

    Marco Platzner

  3. IMEC, Kapeldreef 75, Leuven, Leuven, Belgium

    Serge Vernalde

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© 2004 Springer-Verlag Berlin Heidelberg

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Tiri, K., Verbauwhede, I. (2004). Secure Logic Synthesis. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_125

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  • DOI: https://doi.org/10.1007/978-3-540-30117-2_125

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-22989-6

  • Online ISBN: 978-3-540-30117-2

  • eBook Packages: Springer Book Archive

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