Abstract
As SoC technology use increases, the question arises of how to connect the on-chip components. Current solutions use familiar components (such as busses and direct links) but these have throughput concerns and unnecessarily complicate the system design. This paper introduces the full/empty register pipe (FERP) interface and a collection of IP cores to support it. Along with its dataflow computational model, this interface is extremely well-suited for stream processing — an emerging computational model that is gaining popularity from embedded systems to supercomputers. An example is presented that illustrates how existing IP cores can be easily incorporated and how the resulting IP cores can be combined to perform complex, general stream-based algorithms.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Kapasi, U.J., Dally, W.J., Khailany, B., Owens, J., Rixner, S.: The Imagine stream processor (2002)
Waingold, E., Taylor, M., Srikrishna, D., Sarkar, V., Lee, W., Lee, V., Kim, J., Frank, M., Finch, P., Barua, R., Babb, J., Amarasinghe, S., Agarwal, A.: Baring it all to software: Raw machines. Computer 30, 86–93 (1997)
Suh, J., Kim, E.G., Crago, S.P., Srinivasan, L., French, M.C.: A performance analysis of PIM, stream processing, and tiled processing on memory-intensive signal processing kernels. In: Proceedings of the 30th annual international symposium on Computer architecture, pp. 410–421. ACM Press, New York (2003)
Dally, W.J., Labont, F., Das, A., Hanrahan, P., Ahn, J.H., Gummaraju, J., Erez, M., Jayasena, N., Buck, I., Knight, T.J., Kapasi, U.J.: Merrimac: Supercomputing with streams. In: Proceedings of the 2003 ACM/IEEE conference on Supercomputing, IEEE Computer Society Press, Los Alamitos (2003)
Ciricescu, S., Essick, R., Lucas, B., May, P., Moat, K., Norris, J., Schuette, M., Saidi, A.: The reconfigurable streaming vector processor (RSVPTM). In: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, p. 141. IEEE Computer Society, Los Alamitos (2003)
Ross, C., Bohm, W.: Using FIFOs in hardware-software co-design for fpga based embedded systems. In: IEEE Symposium on FPGAs for Custom Computing Machines, IEEE Computer Society Press, Los Alamitos (2004)
IBM (2004), http://www-3.ibm.com/chips/products/coreconnect/
Altera (2004), http://www.altera.com/products/software/system/products/soc/avalon/features/nio-avalonfeatures.html
Bellows, P., Hutchings, B.: JHDL - an HDL for reconfigurable systems. In: Pocek, K.L., Arnold, J. (eds.) IEEE Symposium on FPGAs for Custom Computing Machines, pp. 175–184. IEEE Computer Society Press, Los Alamitos (1998)
Hazelwood, K., III, W.B.L., Monn, G., Sass, R., Stanzione, D., Underwood, K.D.: Creating applications in RCADE. In: Proceedings of the IEEE Aerospace Conference (1999)
Boyson, B., DeBardeleben, N., Hazelwood, K.: III, W.B.L., Sass, R., Dan Stanzione, J., Underwood, K.D.: A development environment for configurable computing. In: Proceedings of SPIE: Configurable Computing: Technology and Applications, pp. 103–113 (1998)
Nalabalapu, P.K.: Design of a reconfigurable data cache for image processing hardware. Master’s thesis, Clemson University (2003)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Young, J., Sass, R. (2004). FERP Interface and Interconnect Cores for Stream Processing Applications. In: Yang, L.T., Guo, M., Gao, G.R., Jha, N.K. (eds) Embedded and Ubiquitous Computing. EUC 2004. Lecture Notes in Computer Science, vol 3207. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30121-9_28
Download citation
DOI: https://doi.org/10.1007/978-3-540-30121-9_28
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22906-3
Online ISBN: 978-3-540-30121-9
eBook Packages: Springer Book Archive