Abstract
Fat H-Tree is a novel on-chip network topology for a dynamic reconfigurable processor array. It includes both fat tree and torus structure, and suitable to map tasks in a stream processing. For on-chip implementation, folding layout is also proposed. Evaluation results show that Fat H-Tree reduces the distance of H-Tree from 13% to 55%, and stretches the throughput almost three times.
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Yamada, Y., Amano, H., Koibuchi, M., Jouraku, A., Anjo, K., Nishimura, K. (2004). Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. In: Yang, L.T., Guo, M., Gao, G.R., Jha, N.K. (eds) Embedded and Ubiquitous Computing. EUC 2004. Lecture Notes in Computer Science, vol 3207. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30121-9_29
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DOI: https://doi.org/10.1007/978-3-540-30121-9_29
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