Abstract
This paper proposes a new approach for improving the performance of Globally Asynchronous Locally Synchronous (GALS) circuits. This approach takes advantage of the delay dependence of the input vectors to classify input data into several classes. Each class has a clock period associated, in such a way that a suitable clock is selected for each data. This technique has been applied to a GALS pipelined RISC processor based on DLX processor. Several programs were run over this processor performing different classifications, in order to check the viability of this new approach.
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López, S., Garnica, O., Colmenar, J.M. (2004). Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_64
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DOI: https://doi.org/10.1007/978-3-540-30205-6_64
Publisher Name: Springer, Berlin, Heidelberg
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