Skip to main content

Design Exploration Framework Under Impreciseness Based on Register-Constrained Inclusion Scheduling

  • Conference paper
Advances in Computer Science - ASIAN 2004. Higher-Level Decision Making (ASIAN 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3321))

Included in the following conference series:

  • 1165 Accesses

Abstract

In this paper, we propose a design exploration framework which consider impreciseness in design specification. In high-level synthesis, imprecise information is often encountered. Two kinds of impreciseness are considered here: imprecise characteristics of functional units and imprecise design constraints. The proposed design exploration framework is based on efficient scheduling algorithm which considers impreciseness, Register-Constrained Inclusion Scheduling. We demonstrate the effectiveness of our framework by exploring a design solution for a well-known benchmark, Voltera filter. The selected solution meets the acceptability criteria while minimizing the total number of registers.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Ahmad, I., Dhodhi, M.K., Chen, C.Y.R.: Integrated scheduling, allocation and module selection for design-space exploration in high-level synthesis. IEEE Proc.-Comput. Digit. Tech. 142, 65–71 (1995)

    Article  Google Scholar 

  2. Chantrapornchai, C., Sha, E.H., Hu, X.S.: Efficient scheduling for imprecise timing based on fuzzy theory. In: Proc. Midwest Symposium on Circuits and Systems, pp. 272–275 (1998)

    Google Scholar 

  3. Chantrapornchai, C., Sha, E.H., Hu, X.S.: Efficient algorithms for finding highly acceptable designs based on module-utility selections. In: Proceedings of the Great Lake Symposium on VLSI, pp. 128–131 (1999)

    Google Scholar 

  4. Chantrapornchai, C., Sha, E.H.-M., Hu, X.S.: Efficient module selections for finding highly acceptable designs based on inclusion scheduling. J. of System Architecture 11(4), 1047–1071 (2000)

    Article  Google Scholar 

  5. Chantrapornchai, C., Sha, E.H.-M., Hu, X.S.: Efficient acceptable design exploration based on module utility selection. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems 19, 19–29 (2000)

    Article  Google Scholar 

  6. Chantrapornchai, C., Surakumpolthorn, W., Sha, E.H.: Efficient scheduling for design exploration with imprecise latency and register constraints. In: Yang, L.T., Guo, M., Gao, G.R., Jha, N.K. (eds.) EUC 2004. LNCS, vol. 3207, pp. 259–270. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  7. Chantrapornchai, C., Tongsima, S.: Resource estimation algorithm under impreciseness using inclusion scheduling. Intl. J. on Foundation of Computer Science, Special Issue in Scheduling 12(5), 581–598 (2001)

    Google Scholar 

  8. Chaudhuri, S., Bylthe, S.A., Walker, R.A.: An exact methodology for scheduling in 3D design space. In: Proceedings of the 1995 International Symposium on System Level Synthesis, pp. 78–83 (1995)

    Google Scholar 

  9. Chaudhuri, S., Walker, R.: Computing lower bounds on functional units before scheduling. In: Proceedings of the International Symposium on System Level Synthesis, pp. 36–41 (1994)

    Google Scholar 

  10. Dani, A., Ramanan, V., Govindarajan, R.: Register-sensitive software pipelining. In: Proceedings. of the Merged 12th International Parallel Processing and 9th International Symposium on Parallel and Distributed Systems, April 1998, pp. 194–198 (1998)

    Google Scholar 

  11. Eichenberger, A., Davidson, E.S.: Register allocation for predicated code. In: Proceeding of MICRO (1995)

    Google Scholar 

  12. Eichenberger, A.E., Davidson, E.S.: Stage scheduling: A technique to reduce the register requirements of a modulo schedule. In: Proceedings of MICRO-28, pp. 338–349 (1995)

    Google Scholar 

  13. Esbensen, H., Kuh, E.S.: Design space exploration using the genetic algorithm. In: Proceedings of the 1996 International Symposium on Circuits and Systems, pp. 500–503 (1996)

    Google Scholar 

  14. Chen, F., Tongsima, S., Sha, E.H.: Loop scheduling algorithm for timing and memory operation minimization with register constraint. In: Proc. SiP 1998 (1998)

    Google Scholar 

  15. Gupta, K.: Introduction to fuzzy arithmetics. Van Nostrand (1985)

    Google Scholar 

  16. Hammami, O.: Fuzzy scheduling in compiler optimizations. In: Proceedings of the ISUMA-NAFIPS (1995)

    Google Scholar 

  17. Karkowski, I.: Architectural synthesis with possibilistic programming. In: HICSS-28 (January 1995)

    Google Scholar 

  18. Karkowski, I., Otten, R.H.J.M.: Retiming synchronous circuitry with imprecise delays. In: Proceedings of the 32nd Design Automation Conference, San Francisco, CA, pp. 322–326 (1995)

    Google Scholar 

  19. Kaviani, A.S., Vranesic, Z.G.: On scheduling in multiprocess systems using fuzzy logic. In: Proceedings of the International Symposium on Multiple-valued Logic, pp. 141–147 (1994)

    Google Scholar 

  20. Lee, J., Tiao, A., Yen, J.: A fuzzy rule-based approach to real-time scheduling. In: Proc. Intl. Conf. FUZZ-1994, vol. 2 (1994)

    Google Scholar 

  21. Llosa, J., Ayguade, E., Gonzalez, A., Valero, M., Eckhardt, J.: Lifetime-sensitive modulo scheduling in a production environment. IEEE Transactions on Computers 50(3), 234–249 (2001)

    Article  Google Scholar 

  22. Llosa, J., Valero, M., Ayguade, E.: Heuristics for register-constrained software pipelining. In: International Symposium on Microarchitecture, pp. 250–261 (1996)

    Google Scholar 

  23. Mandal, C.A., Chakrabarti, P.O., Ghose, S.: Design space exploration for data path synthesis. In: Proceedings of the10th International Conference on VLSI Design, pp. 166–170 (1996)

    Google Scholar 

  24. Mertins, K., et al.: Set-up scheduling by fuzzy logic. In: Proceedings of the International conference on computer integrated manufacturing and automation technology, pp. 345–350 (1994)

    Google Scholar 

  25. Rabaey, J., Potkonjak, M.: Estimating implementation bounds for real time DSP application specific circuits. IEEE Transactions on Computer-Aided Design of integrated circuits and systems 13(6) (June 1994)

    Google Scholar 

  26. Sharma, A., Jain, R.: Estimating architectural resources and performance for high-level synthesis applications. IEEE Transactions on VLSI systems 1(2), 175–190 (June 1993)

    Article  Google Scholar 

  27. Soma, H., Hori, M., Sogou, T.: Schedule optimization using fuzzy inference. In: Proc. FUZZ-1995, pp. 1171–1176 (1995)

    Google Scholar 

  28. Turksen, I.B., et al.: Fuzzy expert system shell for scheduling. SPIE, 308–319 (1993)

    Google Scholar 

  29. Zadeh, L.A.: The concept of a linguistic variable and its application to approximate reasoning, Part I. Information Science 8, 199–249 (1975)

    Article  MathSciNet  Google Scholar 

  30. Zalamea, J., Llosa, J., Ayguade, E., Valero, M.: Software and hardware techniques to optimize register file utilization in vliw architectures. In: Proceedings of the International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems (IWACT) (July 2001)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2004 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Chantrapornchai, C., Surakumpolthorn, W., Sha, E. (2004). Design Exploration Framework Under Impreciseness Based on Register-Constrained Inclusion Scheduling. In: Maher, M.J. (eds) Advances in Computer Science - ASIAN 2004. Higher-Level Decision Making. ASIAN 2004. Lecture Notes in Computer Science, vol 3321. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30502-6_6

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-30502-6_6

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-24087-7

  • Online ISBN: 978-3-540-30502-6

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics