Abstract
Modular multiplication is fundamental to several public-key cryptography systems such as the RSA encryption system. It is also the most dominant part of the computation performed in such systems. The operation is time consuming for large operands. This paper examines the characteristics of yet another architecture to implement modular multiplication. An experimental modular multiplier prototype is described in VHDL and simulated. The simulation results are presented.
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Nedjah, N., de Macedo Mourelle, L. (2003). Fast Hardware of Booth-Barrett’s Modular Multiplication for Efficient Cryptosystems. In: Yazıcı, A., Şener, C. (eds) Computer and Information Sciences - ISCIS 2003. ISCIS 2003. Lecture Notes in Computer Science, vol 2869. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39737-3_4
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DOI: https://doi.org/10.1007/978-3-540-39737-3_4
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20409-1
Online ISBN: 978-3-540-39737-3
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