Abstract
We introduce Power-Aware Branch Predictor Update (PABU) as a power-efficient branch prediction technique for high performance processors. Our predictor reduces branch prediction energy consumption by eliminating unnecessary branch predictor updates. Our technique relies on information regarding past branch behavior to decide if additional predictor updates result in performance improvements. We avoid updating the predictor for branches where there is already enough information available to correctly predict their outcome. In this work we study energy and performance trade-offs for a subset of SPEC 2k benchmarks. We show that on the average and for an 8-way processor, our technique can reduce branch prediction energy consumption up to 80%compared to a 32k conventional combined branch predictor. This comes with a negligible impact on performance (0.6%max). We show that our technique, on the average, reduces the number of predictor updates by 83%.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Parikh, D., Skadron, K., Zhang, Y., Barcella, M., Stan, M.R.: Power Issues Related to Branch Prediction. In: Proc. Intl. Symposium on High-Performance Computer Architecture (February 2002)
Manne, S., Klauser, A., Grunwald, D.: Pipeline Gating: Speculation Control For Energy Reduction. In: Proc. Intl. Symposium on Computer Architecture (June 1998)
Grunwald, D., Klusser, A., Manne, S., Plezkun, A.: Confidence Estimation for Speculation Control. In: Proc. Intl. Symposium on Computer Architecture (June 1998)
Baniasadi, A., Moshovos, A.: Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors. In: Proc. ISLPED 2001 (August 2001)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectural-Level Power Analysis and Optimization. In: Proc of the 27th Int’l Symp. on Computer Architecture (2000)
Baniasadi, A., Moshovos, A.: Branch Predictor Predcition a Power-Aware Branch Predcitor for High-Performance Processors. In: Proc. ICCD 2002 (September 2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Baniasadi, A. (2003). Power-Aware Branch Predictor Update for High-Performance Processors. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_48
Download citation
DOI: https://doi.org/10.1007/978-3-540-39762-5_48
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
Online ISBN: 978-3-540-39762-5
eBook Packages: Springer Book Archive