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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2799))

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Abstract

We introduce Power-Aware Branch Predictor Update (PABU) as a power-efficient branch prediction technique for high performance processors. Our predictor reduces branch prediction energy consumption by eliminating unnecessary branch predictor updates. Our technique relies on information regarding past branch behavior to decide if additional predictor updates result in performance improvements. We avoid updating the predictor for branches where there is already enough information available to correctly predict their outcome. In this work we study energy and performance trade-offs for a subset of SPEC 2k benchmarks. We show that on the average and for an 8-way processor, our technique can reduce branch prediction energy consumption up to 80%compared to a 32k conventional combined branch predictor. This comes with a negligible impact on performance (0.6%max). We show that our technique, on the average, reduces the number of predictor updates by 83%.

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References

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© 2003 Springer-Verlag Berlin Heidelberg

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Baniasadi, A. (2003). Power-Aware Branch Predictor Update for High-Performance Processors. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_48

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  • DOI: https://doi.org/10.1007/978-3-540-39762-5_48

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-20074-1

  • Online ISBN: 978-3-540-39762-5

  • eBook Packages: Springer Book Archive

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