Abstract
We discuss state of the art and new developments for the path to first time right silicon for low VTH and low power analog design. This article touches on a few of the issues that are essential when starting a low VTH or low power design, where the bottom line is a well controlled process technology and the existence of a comprehensive Process Design Kit with accurate SPICE models which include device mismatch parameters and noise parameters. The necessary process characterisation and the requirements for SPICE modelling are described. In this article state of the art MOS transistor modelling especially in the transition region, noise modelling and device mismatch are discussed with regard to low VTH and low power design.
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Seebacher, E., Rappitsch, G., Höller, H. (2003). Process Characterisation for Low VTH and Low Power Design. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_9
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DOI: https://doi.org/10.1007/978-3-540-39762-5_9
Publisher Name: Springer, Berlin, Heidelberg
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