Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem

Abstract

Large on-chip caches can significantly improve the processor performance. But, they also increase the on-chip energy spent. With the increase in transistor density and decrease in feature sizes, the dominant component of the energy spent is the leakage energy. Since, on-chip caches consume a major portion of the chip’s transistor budget, they are good candidates for the control of leakage energy. In the cache hierarchy, most of the time, the data present at the first level also exists in the lower levels, and hence expends the leakage energy in all the levels that it is present. This paper proposes a mechanism to reduce this leakage energy by exposing the redundancy. In this mechnism, sub-blocks of the L1-data cache are turned off, when the data also exists in the register file. Also, a control mechanism is proposed to turn-off the blocks of L2-cache (in both instruction cache and data cache portions) when the data also exists in L1-cache. An architectural technique is also proposed, to effectively turn-off the portions of the L1 and L2-caches, which are never used for data storage by keeping the cache circuitry initially in low-leakage mode. The effectiveness of the proposed schemes has been demonstrated through cycle accurate simulation using a set of media and SPEC CPU 2000 benchamrks. This mechanism yields an average of about 33% to 36% reduction in the leakage energy for 16 KB to 32 KB dl1-cache and an average of 79% and 86% for 128 KB of dL2 and iL2 caches respectively, albeit with a little performance degradation.