Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation

Abstract

Code size is an important design constraint in cost-sensitive embedded systems, since the amount of available memory is often limited. This constraint motivates dual instruction set processors, which support a reduced instruction set with a smaller instruction length in addition to a normal instruction set. This dual instruction set provides an effective mechanism for code size reduction. However, the code size reduction comes at the price of degraded performance because a program compiled into the reduced instruction set executes a larger number of instructions than the same program compiled into the normal instruction set. Motivated by this observation, we propose a technique that can be used to enable a flexible tradeoff between the code size and execution time of a program by using the two instruction sets selectively for different parts of a program. Our proposed approach determines the instruction set to be used for each basic block using a path-based profitability analysis, so that the execution time of the resulting program is minimized while the code size constraint is satisfied. The results from our experiments verify that the tradeoff relationship exists between a program’s code size and execution time, and further indicate that the proposed technique can effectively exploit this tradeoff to improve performance within the given code size budget.

This work was supported in part by the Ministry of Education under the Brain Korea 21 Project in 2003, and by the Ministry of Science and Technology under the National Research Laboratory program. The ICT at Seoul National University provided research facilities for this study.