Abstract
A chain FeRAM (TM) is a solution for future high-density and high-speed nonvolatile memory. One memory cell consists of one transistor and one ferroelectric capacitor connected in parallel, and one memory cell block consists of a member of cells in series. This configuration realizes a small memory cell of 4 F\(^{2}\) size in the ideal case and a fast random access time. In this chapter, overview and design techniques for chain FeRAM are presented. Not only chain architecture but also several design techniques for realizing 1. high-speed, 2. high-density, and 3. low-voltage operation are discussed. 0.25 micro meter 8 Mb chain FeRAMs using these techniques are demonstrated.
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Takashima, D., Oowaki, Y. Chain \protect\mbox{FeRAMs}. In: Ishiwara, H., Okuyama, M., Arimoto, Y. (eds) Ferroelectric Random Access Memories. Topics in Applied Physics, vol 93. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45163-1_14
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DOI: https://doi.org/10.1007/978-3-540-45163-1_14
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Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40718-8
Online ISBN: 978-3-540-45163-1
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