Abstract
In this paper, an efficient VLSI architecture of full-search variable block size motion estimation (VBSME) suitable for high quality video is proposed. Memory bandwidth in high-quality video is a mainly responsible for throughput limitations and power consumption in VBSME. The proposed architecture is designed for reducing the memory bandwidth by adopting “meander”-like scan for a high overlapped data of the search area and using on-chip memory to reuse the overlapped data. We can reuse the previous candidate block of 98% for the current one and save memory access cycles about 19% in a search range of [-32, +31]. The architecture has been prototyped in Verilog HDL and synthesized by Synopsys Design Compiler with Samsung 0.18um standard cell library. Under a clock frequency of 67MHz, The simulation result shows that the architecture can achieve the real-time processing of 720x576 picture size at 30fps with the search range of [-32~+31].
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© 2006 Springer-Verlag Berlin Heidelberg
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Pyen, SM., Min, KY., Chong, JW. (2006). An Efficient VLSI Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. In: Cham, TJ., Cai, J., Dorai, C., Rajan, D., Chua, TS., Chia, LT. (eds) Advances in Multimedia Modeling. MMM 2007. Lecture Notes in Computer Science, vol 4352. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-69429-8_5
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DOI: https://doi.org/10.1007/978-3-540-69429-8_5
Publisher Name: Springer, Berlin, Heidelberg
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