Abstract
Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor cores, I/O peripherals, a direct memory access (DMA) controller, and off-chip memory. External memory access activities are a major source of energy consumption in embedded systems, and especially in multimedia platforms. In this paper, we focus on the energy dissipated due to the address, data, and control activity on the external bus and supporting logic. We build our external bus power model on top of a cycle-accurate simulation framework that quantifies the bus power based on memory bus state transitions. We select the Analog Devices ADSP-BF533 Blackfin processor as our target architecture model. Using our power-aware external bus arbitration schemes, we can reduce overall external bus power by as much as 18% in video processing applications, and by 14% on average for the test suites studied. Besides reducing power consumption, we also obtained an average bus performance speedup of 21% when using our power-aware arbitration schemes.
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Ning, K., Kaeli, D. (2007). Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers I. Lecture Notes in Computer Science, vol 4050. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71528-3_8
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DOI: https://doi.org/10.1007/978-3-540-71528-3_8
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