Abstract
Aiming for a systematic evaluation of DRAM sense amplifier (SA) performance, the SA is modeled using small signal equivalent circuit approach in order to analyze mismatch effects and to support design robustness concerning technology variations. The statistical mismatch of the SA is replaced by equivalent voltage sources. The switching delay between n- and p-sensing transistors of the SA is also analyzed. This approach supports yield consideration of DRAM sense amplifiers in future technologies.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Sarpeshkar, R., et al.: Mismatch Sensitivity of a Simultaneously Latched CMOS Sense Amplifier. IEEE JSSC 26(10), 1422–1431 (1991)
Kraus, R., et al.: Optimized Sensing Scheme of DRAM’s. IEEE JSSC 24(4), 895–899 (1989)
Van Noije, W.A.M., et al.: Precise Final State Determination of Mismatched CMOS Latches. IEEE JSSC 30(5), 607–611 (1995)
Pelgrom, M.J.M., et al.: Matching properties of MOS transistors. IEEE JSSC 24(5), 1433–1440 (1989)
Bronstein, I.N., Tuinhout, H.P., et al.: Taschenbuch der Mathematik. Verlag Harri Deutsch, Thun (2001)
Grinstead, C.M., et al.: Introduction to Probability: Second Revised edn., Dartmouth College, AMS (1997) ISBN-10: 0-8218-0749-8
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Li, Y., Schneider, H., Schnabel, F., Thewes, R., Schmitt-Landsiedel, D. (2009). Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_13
Download citation
DOI: https://doi.org/10.1007/978-3-540-95948-9_13
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
Online ISBN: 978-3-540-95948-9
eBook Packages: Computer ScienceComputer Science (R0)