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Error-Free Transformation in Rounding Mode toward Zero

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Numerical Validation in Current Hardware Architectures

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5492))

Abstract

In this paper, we provide new error-free transformations for the sum and the product of two floating-point numbers. These error-free transformations are well suited for the CELL processor. We prove that these transformations are error-free, and we perform numerical experiments on the CELL processor comparing these new error-free transformations with the classic ones.

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© 2009 Springer-Verlag Berlin Heidelberg

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Graillat, S., Lamotte, JL., Hong, D.N. (2009). Error-Free Transformation in Rounding Mode toward Zero. In: Cuyt, A., Krämer, W., Luther, W., Markstein, P. (eds) Numerical Validation in Current Hardware Architectures. Lecture Notes in Computer Science, vol 5492. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-01591-5_14

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  • DOI: https://doi.org/10.1007/978-3-642-01591-5_14

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-01590-8

  • Online ISBN: 978-3-642-01591-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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