Abstract
In this paper, we propose an on-chip dc-dc buck converter for fine-grain dynamic voltage scaling (DVS) on a multi-power domain SoC. The proposed circuit converts from the I/O voltage to the required core operating voltage. This regulator is equipped with the programmable output buffer and the switching signal modulator according to the module operating condition. The proposed converter is fabricated with a 65-nm standard CMOS logic process within the area of 5 bonding pads. The maximum power efficiency is over 88%, and the leakage current in the deep stand-by mode is measured only 19 nA.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
The International Technology Roadmap for Semiconductors: Process integration, devices, and structures. 2006 Update (2006)
Hattori, T., Irita, T., Ito, M., Yamamoto, E., Kato, H., Sado, G., Yamada, T., Nishiyama, K., Yagi, H., Koike, T., Tsuchihashi, Y., Higashida, M., Asano, H., Hayashibara, I., Tatezawa, K., Shimazaki, Y., Morino, N., Hirose, K., Tamaki, S., Yoshioka, S., Tsuchihashi, R., Arai, N., Akiyama, T., Ohno, K.: A power management scheme controlling 20 power domains for a single-chip mobile processor. In: ISSCC (IEEE International Solid-State Circuit Conference) (February 2006)
Burd, T.D., Brodersen, R.W.: Energy efficient cmos microprocessor design. In: Proc. 28th Hawaii International Conference of System Sciences (January 1995)
Kuroda, T., Fujita, T., Mita, S., Nagamatu, T., Yoshioka, S., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., Sakurai, T.: A 0.9v 150mhz 10mw 4mm2 2-d discrete cosine transform core processor with variable-threshold-voltage scheme. In: ISSCC (IEEE International Solid-State Circuit Conference) Feburuary (1996)
Nowka, K.J., Carpenter, G.D., MacDonald, E.W., Ngo, H.C., Brock, B.C., Ishii, K., Nguyen, T.Y., Burns, J.L.: A 32-bit powerpc system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. IEEE J. Solid-State Circuits (November 2002)
Lattard, D., Beigné, E., Bernard, C., Bour, C., Fabien Clermidy, Y.D., Durupt, J., Varreau, D., Vivet, P., Pénard, P., Bouttier, A., Berrens, F.: A telecom baseband circuit based on an asynchronous network-on-chip. In: ISSCC (IEEE International Solid-State Circuit Conference) (Feburuary (2007)
Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits. Proceedings of the IEEE (Feburuary 2003)
Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T.: Satoshi, Shigematsu, Yamada, J.: 1-v power supply high-speed digital circuit technology with multithreshold-voltage cmos. IEEE J. Solid-State Circuits (August 1995)
Valentian, A., Beigné, E.: Automatic gate biasing of an sccmos power switch achieving maximum leakage reduction and lowering leakage current variability. IEEE J. Solid-State Circuits (July 2008)
Valentian, A., Beigné, E.: Gate bias circuit for an sccmos power switch achieving maximum leakage reduction. In: ESSCIRC (European Solid-State Circuits Conference) (September 2007)
Beigné, E., Clermidy, F., Durupt, J., Lhermet, H., Miermont, S., Thonnart, Y., Xuan, T.T., Valentian, A., Varreau, D., Vivet, P.: An asynchronous power aware and adaptive noc based circuit. In: IEEE Symposium on VLSI Circuits (June 2008)
Hiraki, M., Ito, T., Fujiwara, A., Ohashi, T., Hamano, T., Noda, T.: A 63-μw standby power microcontroller with on-chip hybrid regulator scheme. IEEE J. Solid-State Circuits (May 2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ichihashi, M., Lhermet, H., Beigné, E., Rothan, F., Belleville, M., Amara, A. (2010). An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_38
Download citation
DOI: https://doi.org/10.1007/978-3-642-11802-9_38
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-11801-2
Online ISBN: 978-3-642-11802-9
eBook Packages: Computer ScienceComputer Science (R0)