Abstract
The theory BV of bit-vectors, i.e. fixed-size arrays of bits equipped with standard low-level machine instructions, is becoming very popular in formal verification. Standard solvers for this theory are based on a bit-level encoding into propositional logic and SAT-based resolution techniques. In this paper, we investigate an alternative approach based on a word-level encoding into bounded arithmetic and Constraint Logic Programming (CLP) resolution techniques. We define an original CLP framework (domains and propagators) dedicated to bit-vector constraints. This framework is implemented in a prototype and thorough experimental studies have been conducted. The new approach is shown to perform much better than standard CLP-based approaches, and to considerably reduce the gap with the best SAT-based BV solvers.
Work partially funded by Agence Nationale de la Recherche (grant ANR-08-SEGI-006).
Chapter PDF
Similar content being viewed by others
Keywords
- Constraint Satisfaction Problem
- Abstract Domain
- Constraint Logic Programming
- Linear Arithmetic
- Arithmetic Constraint
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
Apt, K.R., Wallace, M.: Constraint Logic Programming using Eclipse. Cambridge University Press, New York (2007)
Brummayer, R., Biere, A.: Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays. In: Kowalewski, S., Philippou, A. (eds.) TACAS 2009. LNCS, vol. 5505, pp. 174–177. Springer, Heidelberg (2009)
Biere, A., Cimatti, A., Clarke, E.M., Zhu, Y.: Symbolic model checking without BDDs. In: Cleaveland, W.R. (ed.) TACAS 1999. LNCS, vol. 1579, pp. 193–207. Springer, Heidelberg (1999)
Bruttomesso, R., Cimatti, A., Franzén, A., Griggio, A., Sebastiani, R.: The MathSAT 4 SMT Solver. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, vol. 5123, pp. 299–303. Springer, Heidelberg (2008)
Barray, F., Codognet, P., Diaz, D., Michel, H.: Code-based test generation for validation of functional processor descriptions. In: Garavel, H., Hatcliff, J. (eds.) TACAS 2003. LNCS, vol. 2619, pp. 569–584. Springer, Heidelberg (2003)
Bardin, S., Herrmann, P.: Structural Testing of Executables. In: 1st Int. Conf. on Software Testing, Verification, and Validation, pp. 22–31. IEEE Computer Society, Los Alamitos (2008)
Cousot, P., Cousot, R.: Abstract Interpretation: A Unified Lattice Model for Static Analysis of Programs by Construction or Approximation of Fixpoints. In: 4th ACM Symposium on Principles of Programming Languages, pp. 238–252. ACM, New York (1977)
Cadar, C., Ganesh, V., Pawlowski, P.M., Dill, D.L., Engler, D.R.: EXE: automatically generating inputs of death. In: 13th ACM Conf. on Computer and Communications Security, pp. 322–335. ACM, New York (2006)
Clarke, E.M., Kroening, D., Lerda, F.: A tool for checking ANSI-C programs. In: Jensen, K., Podelski, A. (eds.) TACAS 2004. LNCS, vol. 2988, pp. 168–176. Springer, Heidelberg (2004)
Diaz, D., Codognet, P.: Design and Implementation of the GNU Prolog System. J. Functional and Logic Programming, 2001. EAPLS (2001)
Dechter, R.: Constraint Processing. Morgan Kaufmann, San Francisco (2003)
Ferrandi, F., Rendine, M., Sciuto, D.: Functional verification for SystemC descriptions using constraint solving. In: 5th Conf. on Design, Automation and Test in Europe, pp. 744–751. IEEE Computer Society, Los Alamitos (2002)
Frühwirth, T.: Theory and Practice of Constraint Handling Rules. J. Logic Programming 37(1-3), 95–138 (1998)
Feydy, T., Schutt, A., Stuckey, P.J.: Global difference constraint propagation for finite domain solvers. In: 10th Int. ACM SIGPLAN Conf. on Principles and Practice of Declarative Programming, pp. 226–236. ACM, New York (2008)
Ganesh, V., Dill, D.L.: A Decision Procedure for Bit-Vectors and Arrays. In: Damm, W., Hermanns, H. (eds.) CAV 2007. LNCS, vol. 4590, pp. 519–531. Springer, Heidelberg (2007)
Jussien, N., Rochart, G., Lorca, X.: The CHOCO constraint programming solver. In: CPAIOR 2008 Workshop on Open-Source Software for Integer and Contraint Programming (2008)
Kroening, D., Strichman, O.: Decision Procedures: An Algorithmic Point of View. Springer, Heidelberg (2008)
Leconte, M., Berstel, B.: Extending a CP Solver With Congruences as Domains for Software Verification. In: CP 2006 Workshop on Constraints in Software Testing, Verification and Analysis (2006)
Lecoutre, C., Tabary, S.: Abscon 112: Toward more Robustness. In CSP Solver Competition, held with CP 2008 (2008)
Marre, B., Blanc, B.: Test selection strategies for Lustre descriptions in GATeL. Electr. Notes Theor. Comput. Sci. 111, 93–111 (2005)
Moskewicz, M., Madigan, C., Zhao, Y., Zhang, L., Malik, S.: Chaff: engineering an efficient SAT solver. In: 38th Design Automation Conf., pp. 530–535. ACM, New York (2001)
Manolios, P., Vroon, D.: Efficient circuit to CNF conversion. In: Marques-Silva, J., Sakallah, K.A. (eds.) SAT 2007. LNCS, vol. 4501, pp. 4–9. Springer, Heidelberg (2007)
Sülflow, A., Kühne, U., Wille, R., Große, D., Drechsler, R.: Evaluation of SAT like proof techniques for formal verification of word level circuits. In: 8th IEEE Workshop on RTL and High Level Testing, pp. 31–36. IEEE Computer Society, Los Alamitos (2007)
SMT competition, http://www.smtcomp.org/
Vemuri, R., Kalyanaraman, R.: Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. IEEE Transactions on VLSI Systems 3(2), 201–214 (1995)
Wille, R., Fey, G., Große, D., Eggersglüß, S., Drechsler, R.: SWORD: A SAT like prover using word level information. In: 18th Int. Conf. on Very Large Scale Integration of Systems-on-Chip, pp. 88–93. IEEE, Los Alamitos (2007)
Zeng, Z., Ciesielski, M., Rouzeyre, B.: Functional test generation using Constraint Logic Programming. In: 11th Int. Conf. on Very Large Scale Integration of Systems-on-Chip, pp. 375–387. Kluwer, Dordrecht (2001)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Bardin, S., Herrmann, P., Perroud, F. (2010). An Alternative to SAT-Based Approaches for Bit-Vectors. In: Esparza, J., Majumdar, R. (eds) Tools and Algorithms for the Construction and Analysis of Systems. TACAS 2010. Lecture Notes in Computer Science, vol 6015. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12002-2_7
Download citation
DOI: https://doi.org/10.1007/978-3-642-12002-2_7
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-12001-5
Online ISBN: 978-3-642-12002-2
eBook Packages: Computer ScienceComputer Science (R0)