Power-Aware Multi-objective Evolutionary Optimization for Application Mapping on NoC Platforms

Abstract

Network-on-chip (NoC) are considered the next generation of communication infrastructure, which will be omnipresent in different environments. In the platform-based design methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. The selection of the most suited set of IPs as well as their physical mapping onto the NoC to implement efficiently the application at hand are two hard combinatorial problems. In this paper, we propose an innovative power-aware multi-objective evolutionary algorithm to perform the assignment and mapping stages of a platform-based NoC design synthesis tool. Our algorithm can use one of the well-known multi-objective evolutionary algorithms NSGA-II and microGA as kernel. The optimization is driven by the required area and the imposed execution time considering that the decision maker’s is the power consumption of the implementation.