Abstract
Packet filters are essential for most areas of recent information network technologies. While high-end expensive routers and firewalls are implemented in hardware-based, flexible and cost-effective ones are usually in software-based solutions using general-purpose CPUs but have less performance. The authors have studied the methods of applying code optimization techniques to the packet filters executing on a single core processor. In this paper, by utilizing the multi-core processor Cell Broadband Engine with software pipelining, we construct a parallelized and SIMDed packet filter 40 times faster than the naive C program filter executed on a single core.
This work was supported in part by Hitachi, Ltd. and National Institute of Information and Communications Technology.
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Yamashita, Y., Tsuru, M. (2010). Implementation and Evaluation of Fast Parallel Packet Filters on a Cell Processor. In: Zavoral, F., Yaghob, J., Pichappan, P., El-Qawasmeh, E. (eds) Networked Digital Technologies. NDT 2010. Communications in Computer and Information Science, vol 87. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-14292-5_22
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DOI: https://doi.org/10.1007/978-3-642-14292-5_22
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