Abstract
Research in computational aspects and algorithm optimizations help design tools to acceleration the execution of algorithms. Cost and availability of FPGA design boards have driven number of computations per second close to the general-purpose model of CPUs. In this chapter, we study the effects of algorithms with the knowledge of the underlying computing model for getting consistent and coherent view of the sensed data. The computing model uses uniprocessor, multiprocessor and acceleration using pipeline and data-path forwarding with Byzantine fault-tolerance. The pre-processing approach of the modified algorithm for sparse sensing gives better consistency and the application based calibration allowing coherent view of the data and at the same time reduces the total power consumption. This is analogous to the needle in a hay stack. The STACK implementation runs 4 times faster than the normal program based optimizations for static and dynamic scheduling.
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Iyer, V., Iyengar, S.S., Murthy, G.R., Srinathan, K., Srinivas, M.B., Govindarajulu, R. (2011). STACK: Sparse Timing of Algorithms Using Computational Knowledge. In: Mukhopadhyay, S.C., Lay-Ekuakille, A., Fuchs, A. (eds) New Developments and Applications in Sensing Technology. Lecture Notes in Electrical Engineering, vol 83. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17943-3_16
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DOI: https://doi.org/10.1007/978-3-642-17943-3_16
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