Abstract
As technology advances, new hardware approaches are proposed to speed up software execution. However, every new added hardware feature must not change the underlying instruction set architecture (ISA), in order to avoid adaptation or recompilation of existing code. As binary translation allows the execution of binary codes of already compiled applications on different architectures, it opens new possibilities for designers, previously tied to a specific ISA and all its legacy hardware issues. The problem with binary translation is its inherent performance penalty: it will always take more cycles than the simple execution on the native machine. To address that, we propose a new mechanism based on a dynamic two-level binary translation system. While the first level is responsible for the BT de facto (in our first implemented case study, X86 to MIPS translations), the second level optimizes the already translated instructions to be executed on a dynamically adaptable reconfigurable architecture. This way, both software portability and performance are maintained.
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Junior, J.F., Rutzig, M.B., Beck, A.C.S., Carro, L. (2011). Towards an Adaptable Multiple-ISA Reconfigurable Processor. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_18
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DOI: https://doi.org/10.1007/978-3-642-19475-7_18
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