Abstract
This paper presents a layered LDPC decoder for WiMAX applications. A novel architecture based on parallel check node is proposed providing scalability in terms of supporting multiple code rates, block lengths and parallelisms to realize a high throughput LDPC decoder. The proposed design is fully compliant to support all 114 codes defined by WiMax standard. The IP core has been implemented using 130 nm standard cell ASIC technology. The proposed decoder achieves a throughput of 240 Mbps at 300 MHz and occupies a chip area of 2.76 mm 2.
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Awais, M., Singh, A., Masera, G. (2011). Scalable, High Throughput LDPC Decoder for WiMAX (802.16e) Applications. In: Abraham, A., Lloret Mauri, J., Buford, J.F., Suzuki, J., Thampi, S.M. (eds) Advances in Computing and Communications. ACC 2011. Communications in Computer and Information Science, vol 191. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22714-1_39
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DOI: https://doi.org/10.1007/978-3-642-22714-1_39
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