Abstract
The interdependency of setup and hold times of flipflops in digital circuits needs to be considered in order to obtain more accurate results of timing analysis. In this paper, an iterative STA method is developed based on a new modeling of flipflop timing behavior. Two basic problems are solved: whether a circuit can work at a given clock period, and how the minimal clock period is determined. Experimental results show that a reduction of the clock period by 3.3% can be achieved compared to traditional STA method.
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References
Lang, A., Bergler, S.: Method and apparatus for circuit verification of meeting setup and hold time requirements (Verfahren und Vorrichtung zum Ueberpruefen einer Schaltung auf Einhaltung von Setup- und Holdzeiten). Patent DE102004044668A1 (2004)
Salman, E., Dasdan, A., Taraporevala, F., Kucukcakar, K., Friedman, E.G.: Exploiting setup-hold-time interdependence in static timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(6), 1114–1125 (2007)
Salman, E., Dasdan, A., Taraporevala, F., Kucukcakar, K., Friedman, E.G.: Pessimism reduction in static timing analysis using interdependent setup and hold times. In: ISQED 2006, pp. 159–164 (2006)
Srivastava, S., Roychowdhury, J.: Interdependent latch setup/hold time characterization via Euler-Newton curve tracing on state-transition equations. In: DAC 2007, pp. 136–141 (2007)
Srivastava, S., Roychowdhury, J.: Independent and interdependent latch setup/hold time characterization via Newton-Raphson solution and Euler curve tracking of state-transition equations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(5), 817–830 (2008)
Hatami, S., Abrishami, H., Pedram, M.: Statistical timing analysis of flip-flops considering codependent setup and hold times. In: GLSVLSI 2008, pp. 101–106 (2008)
Sakallah, K.A., Mudge, T.N., Olukotun, O.A.: Analysis and design of latch-controlled synchronous digital circuits. In: DAC 1990, pp. 111–117 (1990)
Gabara, T., Cyr, G., Stroud, C.: Metastability of CMOS master/slave flip-flops. In: CICC 1991, pp. 29.4/1–29.4/6. (1991)
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Chen, N., Li, B., Schlichtmann, U. (2011). Iterative Timing Analysis Considering Interdependency of Setup and Hold Times. In: Ayala, J.L., GarcÃa-Cámara, B., Prieto, M., Ruggiero, M., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2011. Lecture Notes in Computer Science, vol 6951. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24154-3_8
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DOI: https://doi.org/10.1007/978-3-642-24154-3_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-24153-6
Online ISBN: 978-3-642-24154-3
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