Abstract
The problem considered in this chapter is this: Having designed an asynchronous circuit according to a given word-recognition tree, or flow table, we next want to verify our logic design by developing a minimal length events graph with which to completely test the circuit’s input–output behaviour. In the literature, this is usually referred to as functional testing. In general, the problem is seen as unsolvable. Mead and Conway (1980) put it this way: ‘Complete functional testing of complex systems with internal sequencing is not possible in general, and most integrated system chips manufactured, even at 1978 levels of complexity, are not economically testable for even a small fraction of their possible internal states.’
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References
Brzozowski, J.A., Yoeli, M.: Digital Networks. Prentice Hall, Englewood Cliffs (1976)
Brzozowski, J.A., Seger, C.-J.H.: Asynchronous Circuits. Springer, New York (1995)
Caldwell, S.H.: Switching Circuits and Logic Design. Wiley, New York (1958)
Clare, C.R.: Designing Logic Systems using State Machines. McGrew-Hill Book Company, New York (1973)
Dietmeyer, D.L.: Logic Design of Digital Systems. Allyn and Bacon, Boston (1971)
Eilenberg, S., Elgot, C.C.: Recursiveness. Academic Press, New York (1970)
Fasol, K.H., Vingron, P.: Synthese Industrieller Steuerungen. R. Oldenbourg Verlag, München (1975)
Harrison, M.A.: Introduction to Switching and Automata Theory. McGraw-Hill Book Company, New York (1965)
Kohavi, Z.: Switching and Finite Automata Theory. McGraw-Hill Book Company, New York (1970)
Krieger, M.: Basic Switching Circuit Theory. McGraw-Hill Book Company, New York (1969)
McCluskey, E.J.: Logic Design Principles. Prentice Hall, London (1986)
Mead, C., Conway, L.: Introduction to VLSI Systems. Addison-Wesley, Reading Massachusetts (1980)
Muroga, S.: Logic Design and Switching Theory. Wiley, New York (1979)
Pessen, D.W.: Ìndustrial Automation. Wiley, New York (1989)
Unger, S.H.: Asynchronous Sequential Switching Circuits. Wiley, New York (1969)
Vingron, S.P.: Switching Theory. Springer, Berlin (2004)
Zander, H.-J.: Entwurf von Folgeschaltungen. VEB Verlag Technik, Berlin (1974) Selected Papers
Ashenhurst, R.A.: The decomposition of switching functions. In: Proceedings of an International Symposium on the Theory of Switching, April 2–5, 1957. Annals of the Compotation Laboratory of Harvard University, vol. 29, pp. 74–116. Harvard University Press (1959)
Huffman, D.A.: The synthesis of sequential switching circuits. J. Frankl. Inst. 257:161–190 (1954) and 275–303 (1954)
Huffman, D.A.: A study of memory requirements of sequential switching circuits. Massachusetts Institute of Technology, Research Laboratory of Electronics, Technical Report No. 293, April 1955
Huffman, D.A.: The design and use of Hazard-Free switching networks. J. Assoc. Comput. Mach. 4:47–62 (1957)
Karnaugh, M.: The map method for synthesis of combinational logic circuits. Trans. AIEE, Part I, 72(9):593–599 (1953)
McCluskey, E.J.: Minimisation of boolean functions. Bell Syst. Tech. J. 35(6):1417–1445 (1956)
Mealy, G.H.: A method for synthesizing sequential circuits. Bell Syst. Tech. J. 34(5):1045–1079 (1955)
Medvedev, I.T.: On a class of events representable in a finite automaton, pp. 385–401. Avtomaty, Moscow (1956). English translation in MIT Lincoln Laboratory Group Report, pp. 34–73, June 1958
Moore, E.F.: Gedankenexperiments on sequential machines. In: Shannon, C.E., McCarthy, J., Ashby, W.R. (eds.) Automata Studies. Princeton University Press, Princeton (1956)
Quine, W.V.: The problem of simplifying truth functions. Am. Math. Mon. 59:521–531 (1952)
Quine, W.V.: A way to simplify truth functions. Am. Math. Mon. 63:627–631 (1955)
Shannon, C.E.: A symbolic analysis of relays and switching circuits. Trans. AIEE 57:713–723 (1938)
Tracey, J.H.: Internal state assignment for asynchronous sequential circuits. IEEE Trans. Electron. Comput. EC-15:551–560 (1966)
Unger, S.H.: Hazards and delays in asynchronous sequential circuits. IRE Trans. Circuit Theory CT-6:12–25 (1959)
Veitch, E.W.: A chart method for simplifying truth functions. Proceedings of Pittsburgh Association for Computing Machinery, University of Pittsburgh, May 1952
Vingron, P.: Coherent design of sequential circuits. IEE Proc. 130E:190–201 (1983)
Zhegalkin, I.I.: The French title of the Russian original is Gégalkin I. I.: ‘Sur le calcul des propositions dans la logique symbolique’. Mat. Sbornik 34:9–28 (1927)
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Vingron, S.P. (2012). Verifying a Logic Design. In: Logic Circuit Design. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27657-6_18
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