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Speed and Size-Optimized Implementations of the PRESENT Cipher for Tiny AVR Devices

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  • First Online:
Radio Frequency Identification (RFIDSec 2013)

Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 8262))

Abstract

This paper presents high-speed and low-size assembly implementations of the 80-bit version of the PRESENT cipher for the (Tiny)AVR family of microcontrollers. We report new speed and size records for our implementations, with the speed-optimized version achieving a full encryption in 8721 clock cycles and the size-optimized version compressing the cipher down to 272 bytes; the previous state of the art for (Tiny)AVR achieved 10723 clock cycles for encryption with a size of 936 bytes. Along with the two implementation extrema (speed and size optimized versions), we offer insight into techniques and representations that show the speed/area tradeoffs and provide intermediate solutions for various configurations.

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Notes

  1. 1.

    Benchmarking was performed on ATmega2560.

  2. 2.

    Additional external SRAM is not an option, since it is at least as slow as flash memory.

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Authors and Affiliations

  1. Radboud Universiteit Nijmegen, Nijmegen, The Netherlands

    Konstantinos Papagiannopoulos & Aram Verstegen

Authors
  1. Konstantinos Papagiannopoulos
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  2. Aram Verstegen
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Correspondence to Aram Verstegen .

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Editors and Affiliations

  1. Technische Universität Graz, Graz, Austria

    Michael Hutter

  2. Graz University of Technology, Graz, Austria

    Jörn-Marc Schmidt

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Papagiannopoulos, K., Verstegen, A. (2013). Speed and Size-Optimized Implementations of the PRESENT Cipher for Tiny AVR Devices. In: Hutter, M., Schmidt, JM. (eds) Radio Frequency Identification. RFIDSec 2013. Lecture Notes in Computer Science(), vol 8262. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41332-2_11

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  • DOI: https://doi.org/10.1007/978-3-642-41332-2_11

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-41331-5

  • Online ISBN: 978-3-642-41332-2

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