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PROPAN: Ein retargierbares System für Postpassoptimierungen und -analysen

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Informatik 2000

Part of the book series: Informatik aktuell ((INFORMAT))

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Zusammenfassung

In diesem Artikel wird ein System zur Generierung maschinensensitiver Postpassoptimierer und -analysatoren auf Assemblerebene vorgestellt, das speziell im Hinblick auf hochleistungsfähige Optimierungen für irreguläre Architekturen entworfen wurde. Für jede Zielarchitektur wird ein phasengekoppelter Codeoptimierer zur Durchführung integrierter globaler Instruktionsanordnung, Registerzuweisung und Ressourcenallokation auf der Basis ganzzahliger linearer Programmierung (ILP) generiert. Alle relevanten Informationen über die Zielarchitektur werden in der Maschinenbeschreibungssprache Tdl spezifiziert. Die ganzzahligen linearen Programme können entweder exakt oder durch Einsatz ILP-basierter Approximationen gelöst werden, wodurch die Berechnung hochqualitativer Lösungen in akzeptabler Zeit ermöglicht wird. Die Leistungsfähigkeit dieses Ansatzes wird durch eine Reihe praktischer Experimente belegt.

Mitglied des Graduiertenkollegs „Effizienz und Komplexität von Algorithmen und Rechenanlagen“ (gefördert durch die DFG).

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Literatur

  1. Analog Devices. ADSP-2106x SHARC User’s Manual, 1995.

    Google Scholar 

  2. S. Arya. An Optimal Instruction Scheduling Model for a Class of Vector Processors. IEEE Transactions on Computers, 1985.

    Google Scholar 

  3. S. Bashford and R. Leupers. Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths. Design Automation for Embedded Systems, pages 1–50, 1999.

    Google Scholar 

  4. F. Bodin, Z. Chamski, E. Rohou, and A. Seznec. Functional Specification of SALTO: A Retargetable System for Assembly Language Transformation and Optimization, rev. 1.00 beta. INRIA, 1997.

    Google Scholar 

  5. E. Farquhar and E. Hadad. TriCore Architecture Manual. Siemens AG, 1997.

    Google Scholar 

  6. A. Faut h, J. Van Praet, and M. Freericks. Describing Instruction Set Processors Using nML. In Proceedings of the EDAC, pages 503–507. IEEE, 1995.

    Google Scholar 

  7. C. Ferdinand. Cache Behavior Prediction for Real-Time Systems. PhD thesis, Saarland University, 1997.

    Google Scholar 

  8. C. Ferdinand, D. Kästner, M. Langenbach, F. Martin, M. Schmidt, J. Schneider, J. Theiling, S. Thesing, and R. Wilhelm. Run-Time Guarantees for Real-Time Systems — The USES Approach. Proceedings of the ATPS, 1999.

    Google Scholar 

  9. J.A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions on Computers, pages 478–490, 1981.

    Google Scholar 

  10. C.H. Gebotys and M.I. Elmasry. Global Optimization Approach for Architectural Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1266–1278, 1993.

    Google Scholar 

  11. R. Govindarajan, Erik R. Altman, and Guang R. Gao. A Framework for Resource Constrained Rate Optimal Software Pipelining. IEEE Transactions on Parallel and Distributed Systems, (11), 1996.

    Google Scholar 

  12. G. Hadjiyiannis. ISDL: Instruction Set Description Language Version 1.0. Technical report, MIT RLE, 1998.

    Google Scholar 

  13. A. Halambi, P. Grun, V. Ganesh, Khare A., N. Dutt, and A. Nicolau. EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Re-targetability. DATE, 1999.

    Google Scholar 

  14. S. Hanono and S. Devadas. Instruction Scheduling, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the D AC. ACM, 1998.

    Google Scholar 

  15. ILOG S.A. ILOG CPLEX 6.5 User’s Manual, 1999.

    Google Scholar 

  16. D. Kästner. Retargetable Code Optimization by Integer Linear Programming. PhD thesis, Saarland University, 2000. To appear.

    Google Scholar 

  17. D. Kästner. TDL: A Hardware and Assembly Description Language. Technical report, Transferbereich 14, Saarland University, 2000.

    Google Scholar 

  18. D. Kästner and M. Langenbach. Integer Linear Programming vs. Graph-Based Methods in Code Generation. Technical report, Saarland University, 1998.

    Google Scholar 

  19. D. Kästner and M. Langenbach. Code Optimization by Integer Linear Programming. In Proceedings of the CC, pages 122–136, 1999.

    Google Scholar 

  20. D. Kästner and S. Thesing. Cache Sensitive Pre-Runtime Scheduling. In Proceedings of the LCTES Workshop, 1998.

    Google Scholar 

  21. Daniel Kästner. Instruktionsanordnung und Registerallokation auf der Basis ganzzahliger linearer Programmierung für den digitalen Signalprozessor ADSP-2106x. Master’s thesis, Saarland University, 1997.

    Google Scholar 

  22. Kästner, D. and Wilhelm, R. Operations research methods in compiler backends. Mathematical Communications, 1999.

    Google Scholar 

  23. M. Langenbach. CRL — A Uniform Representation for Control Flow. Technical report, Transferbereich 14, Saarland University, November 1998.

    Google Scholar 

  24. R. Leupers. Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, 1997.

    Book  MATH  Google Scholar 

  25. R. Lipsett, C. Schaefer, and C. Ussery. VHDL: Hardware Description and Design. Kluwer Academic Publishers, 12. edition, 1993.

    Google Scholar 

  26. P. Marwedel and G. Goossens. Code Generation for Embedded Processors. Kluwer, 1995.

    Google Scholar 

  27. S. Novack and A. Nicolau. Mutation scheduling: A Unified Approach to Compiling for fine-grain Parallelism. In Languages and Compilers for Parallel Computing, pages 16–30. Springer LNCS, 1994.

    Google Scholar 

  28. L. Nowak. Graph Based Retargetable Microcode Compilation in the MIMÓLA Design System. 20th Annual Workshop on Microprogramming, pages 126–132, 1987.

    Chapter  Google Scholar 

  29. Philips Electronics North America Corporation. TriMedia TM1000 Preliminary Data Book, 1997.

    Google Scholar 

  30. J. Ruttenberg, G.R. Gao, A. Stoutchinin, and W. Lichtenstein. Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler. Proceedings of the PLDI, pages 1–11, 1996.

    Google Scholar 

  31. M.A.R. Saghir, P. Chow, and C.G. Lee. Exploiting Dual Data-Memory Banks in Digital Signal Processors. Proceedings of the ASPLOS, 1996.

    Google Scholar 

  32. A. Sudarsanam. Code Optimization Libraries For Retargetable Compilation For Embedded Digital Signal Processors. PhD thesis, University of Princeton, 1998.

    Google Scholar 

  33. Texas Instruments. TMS320C62xx Programmer’s Guide, 1997.

    Google Scholar 

  34. R. Wilhelm and D. Maurer. Compiler Design. Addison-Wesley, 1995.

    MATH  Google Scholar 

  35. H.P. Williams. Model Building in Mathematical Programming. John Wiley and Sons, New York, 3. edition, 1993.

    Google Scholar 

  36. L. Zhang. SILP. Scheduling and Allocating with Integer Linear Programming. PhD thesis, Saarland University, 1996.

    Google Scholar 

  37. V. Zivojnovic, J. M. Velarde, C. Schläger, and H. Meyr. DSPSTONE: A DSP-Oriented Benchmarking Methodology. In Proceedings of the International Conference on Integrated Systems for Signal Processing, 1994.

    Google Scholar 

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Kästner, D. (2000). PROPAN: Ein retargierbares System für Postpassoptimierungen und -analysen. In: Mehlhorn, K., Snelting, G. (eds) Informatik 2000. Informatik aktuell. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-58322-3_17

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  • DOI: https://doi.org/10.1007/978-3-642-58322-3_17

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67880-9

  • Online ISBN: 978-3-642-58322-3

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