Skip to main content
SpringerLink
Log in

An Analytical Cache—Model for Multiprocessor Systems

  • Conference paper
Messung, Modellierung und Bewertung von Rechen- und Kommunikationssystemen

Part of the book series: Informatik aktuell ((INFORMAT))

  • 38 Accesses

Abstract

A basic cache model for multiprocessor systems is derived and solved in closed form. While details of hardware architecture, cache-coherence protocol, and cache-block replacement strategy are neglected, the results give clear insight in the important dependencies of cache-performance on cache size, number of processors, mixture, and reference characteristics of the tasks contributing to the workload.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 54.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 69.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Agarwal, A., Horowitz, M., Hennessy, J.: An Analytical Cache Model. ACM Trans. Comp. Syst. 7 (1989) 184–215

    Google Scholar 

  2. Agarwal, A.: Performance Tradeoffs in Multithreaded Processors. IEEE Trans. Par. Distr. Syst. 3 (1992) 525–539

    Article  Google Scholar 

  3. Aven, O.I., Coffmann, E.G.Jr., Kogan, Y.A.: Stochastic Analysis of Computer Storage. D. Reidel Publishing Company, Dordrecht (1987)

    MATH  Google Scholar 

  4. Rao, G.S.: Performance Analysis of Cache Memories. J. ACM 25 (1978) 378–395

    Article  MATH  Google Scholar 

  5. Smith, A.J.: Cache Memories. ACM Computing Surveys 14 (1982) 473–530

    Article  Google Scholar 

  6. Smith, A. J.: Cache Evaluation and the Impact of Workload Choice. 12th Int. Symp. on Computer Architecture (1985) 64–73

    Google Scholar 

  7. Smith, A.J.: Second Bibliography on Cache Memories. Comput. Archit. News 19 (1991) 154–182

    Article  Google Scholar 

  8. Strecker, W.D.: Transient Behavior of Cache Memories. ACM TVans. Comp. Syst. 1 (1983) 281–293

    Google Scholar 

  9. Thiebaut, D., Stone, H.S.: Footprints in the Cache. ACM Trans. Comp. Syst. 5 (1987) 305–329

    Google Scholar 

  10. Singh, J.P., Stone, H.S., Thiebaut, D.F.: A Model of Workloads and its Use in Miss-Rate Prediction for Fully Associative Caches. IEEE Trans. Comput. 41 (1992) 811–825

    Article  Google Scholar 

  11. Kogan, Ya.A., Boguslavsky, L.B.: Asymptotic Analysis of Memory Interference in Multiprocessors with Private Cache Memories. Performance Evaluation 5 (1985) 97–114

    Article  MathSciNet  Google Scholar 

  12. Patel, J.H.: Analysis of Multiprocessors with Private Cache Memories. IEEE Trans. Comp. C-31 (1982) 296–304

    Google Scholar 

  13. Squillante, M.S., Lazowska, E.D.: Using Processor-Cache Affinity Information in Shared-Memory Multiprocessor Scheduling. IEEE Trans. Par. Distr. Syst. 4 (1993) 131–143

    Article  Google Scholar 

  14. Gecsei, J., Slutz, D.R., Traiger, I.L.: Evaluation Techniques for Storage Hierarchies. IBM Syst. J. 2 (1970) 78–117

    Google Scholar 

  15. Bussert, W.: LRU-Stack Analyse von CPU-Referenzstrings. Siemens Nixdorf internal report (1992) in german For example: Kuntz, J.-M., Etiemble, D., Syre, J.-C.: Performance Evaluation of Cache Memories in Tightly Coupled Multiprocessor Systems. Proceedings of PARLE’92, Paris, 15–18 June 1992, Springer, Berlin (1992) 735–750

    Google Scholar 

  16. Wilson, A.W.Jr.: Multiprocessor Cache Simulation Using Hardware Collected Address Traces. 23th Hawaii Int. Conf. on Syst. Science (1990) 252–260

    Google Scholar 

  17. Franklin, M.A., Gupta, R.K.: Computation of Page Fault Probability from Program Transition Diagram. Comm. ACM 17 (1974) 186–196

    Article  MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Siemens Nixdorf Informationssysteme AG, Otto-Hahn-Ring 6, 81739, München, Germany

    Thomas Delica

Authors
  1. Thomas Delica
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Lehrstuhl für Kommunikationsnetze, RWTH Aachen, Kopernikusstr. 16, 52074, Aachen, Germany

    B. Walke

  2. Lehrstuhl für Informatik IV, RWTH Aachen, Ahornstr. 55, 52074, Aachen, Germany

    O. Spaniol

  3. Rheinisch-Westfälische Technische Hochschule Aachen, Germany

    O. Spaniol

Rights and permissions

Reprints and permissions

Copyright information

© 1993 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Delica, T. (1993). An Analytical Cache—Model for Multiprocessor Systems. In: Walke, B., Spaniol, O. (eds) Messung, Modellierung und Bewertung von Rechen- und Kommunikationssystemen. Informatik aktuell. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-78495-8_28

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-78495-8_28

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-57201-5

  • Online ISBN: 978-3-642-78495-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation