Abstract
This work describes an integration of logic within the Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) framework. For memory, a minimum separation between the cells is required to ensure bit-to-bit independency. For logic that relies on magnetostatic coupling, a maximum separation is allowed between magnetic cells for effective computation. Integration of the two functionalities therefore requires meeting the orthogonal spatial needs of separation. In this work the technological challenges of this integration are first described followed by the specifications of the new STT-MRAM based logic-in-memory architecture. How a spin transfer torque based control, also called clock, can tune the architecture between logic and memory modes is next described. A reference free variability tolerant differential read scheme leveraging the integration is presented. This logic-in-memory framework is also an integration between magnetic and CMOS planes. Finally, a logic partitioning between the two planes is described that can significantly improve the performance metrics.
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References
Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y., Wong, H.-S.P.: Device scaling limits of Si MOSFET’s and their application dependencies. Proc. IEEE 89(3), 259–288 (2001)
Slonczewski, J.C.: Current-driven excitation of magnetic multilayers. J. Magn. Magn. Mater. 159(1), L1–L7 (1996)
Parkin, S.S., Kaiser, C., Panchula, A., Rice, P.M., Hughes, B., Samant, M., Yang, S.-H.: Giant tunnelling magnetoresistance at room temperature with MgO (100) tunnel barriers. Nat. Mater. 3(12), 862–867 (2004)
Cowburn, R., Welland, M.: Room temperature magnetic quantum cellular automata. Science 287(5457), 1466–1468 (2000)
Imre, A., Csaba, G., Ji, L., Orlov, A., Bernstein, G.H., Porod, W.: Majority logic gate for magnetic quantum-dot cellular automata. Science 311(5758), 205–208 (2006)
Salahuddin, S.: Current induced switching of ferromagnets for low-power memory applications. In: ISQED Symposium, Tutorial (2011)
Zhu, J.-G.J., Park, C.: Magnetic tunnel junctions. Mater. Today 9(11), 36–45 (2006)
Yuasa, S., Djayaprawira, D.: Giant tunnel magnetoresistance in magnetic tunnel junctions with a crystalline MgO (0 0 1) barrier. J. Phys. D: Appl. Phys. 40(21), R337 (2007)
Thomson, W.: Tunneling between ferromagnetic films. Proc. R. Soc. Lond. 8, 546 (1856)
Julliere, M.: Tunneling between ferromagnetic films. Phys. Lett. A 54(3), 225–226 (1975)
Yuasa, S., Fukushima, A., Kubota, H., Suzuki, Y., Ando, K., et al.: Giant tunneling magnetoresistance up to 410% at room temperature in fully epitaxial Co/MgO/Co magnetic tunnel junctions with bcc Co (001) electrodes. Appl. Phys. Lett. 89(4), 42505–42505 (2006)
Maekawa, S. (ed.): Concepts in Spin Electronics. Oxford Science Publications, Oxford (2006)
Lin, C., Kang, S., Wang, Y., Lee, K., Zhu, X., Chen, W., Li, X., Hsu, W., Kao, Y., Liu, M., et al.: 45 nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell. In: 2009 IEEE International Electron Devices Meeting (IEDM), pp. 1–4. IEEE (2009)
Chen, E., Apalkov, D., Diao, Z., Driskill-Smith, A., Druist, D., Lottis, D., Nikitin, V., Tang, X., Watts, S., Wang, S., et al.: Advances and future prospects of spin-transfer torque random access memory. IEEE Trans. Magn. 46(6), 1873–1878 (2010)
Vacca, M., Graziano, M., Zamboni, M.: Majority voter full characterization for nanomagnet logic circuits. IEEE Trans. Nanotechnol. 11(5), 940–947 (2012)
Niemier, M., Alam, M., Hu, X., Bernstein, G., Porod, W., Putney, M., DeAngelis, J.: Clocking structures and power analysis for nanomagnet-based logic devices. In: ISLPED, pp. 26–31. ACM, New York (2007)
Graziano, M., Vacca, M., Chiolerio, A., Zamboni, M.: An NCL-HDL snake-clock-based magnetic QCA architecture. IEEE Trans. Nanotechnol. 10(5), 1141–1149 (2011)
Pulecio, J.F., Bhanja, S.: Magnetic cellular automata coplanar cross wire systems. J. Appl. Phys. 107(3), 034308–034308-5 (2010)
Cowburn, R., Adeyeye, A., Welland, M.: Controlling magnetic ordering in coupled nanomagnet arrays. New J. Phys. 1(1), 16 (1999)
Kumari, A., Bhanja, S.: Landauer clocking for magnetic cellular automata (MCA) arrays. IEEE Trans. Very Large Scale Integr. VLSI Syst. 19(4), 714–717 (2011)
Csaba, G., Lugli, P., Csurgay, A., Porod, W.: Simulation of power gain and dissipation in field-coupled nanomagnets. J. Comput. Electron. 4(1), 105–110 (2005)
Das, J., Alam, S.M., Bhanja, S.: Low power CMOS-magnetic nano-logic with increased bit controllability. In: 2011 11th IEEE Conference on Nanotechnology (IEEE-NANO), pp. 1261–1266. IEEE (2011)
Das, J., Alam, S., Bhanja, S.: Ultra-low power hybrid CMOS-magnetic logic architecture. IEEE TCAS-I 59, 2008–2016 (2012)
Das, J., Alam, S.M., Bhanja, S.: Nanoelectronic Device Applications Handbook, Chap. 60, vol. 16, 1st edn. CRC Press Llc, Boca Raton (2013)
International technology roadmap for semiconductor (2009)
Donahue, M., Porter, D.: Oommf user’s guide, version 1.0, interagency report nistir 6376. NIST, Gaithersburg, MD (1999)
Scheinfein, M.R.: LLG micromagnetics simulator
Karunaratne, D.K., Bhanja, S.: Study of single layer and multilayer nano-magnetic logic architectures. J. Appl. Phys. 111(7), 07A928–07A928-3 (2012)
Das, J., Alam, S., Bhanja, S.: Low power magnetic quantum cellular automata realization using magnetic multi-layer structures. IEEE JETCAS 1, 267–276 (2011)
Das, J., Alam, S.M., Bhanja, S.: Non-destructive variability tolerant differential read for non-volatile logic. In: Proceedings of the 55th International Midwest Symposium on Circuits and Systems (2012)
Pulecio, J., Pendru, P., Kumari, A., Bhanja, S.: Magnetic cellular automata wire architectures. IEEE Trans. Nanotechnol. 10(6), 1243–1248 (2011)
Bhanja, S., Pulecio, J.: A review of magnetic cellular automata systems. In: 2011 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2373–2376 (2011)
Dingler, A., Niemier, M.T., Hu, X.S., Lent, E.: Performance and energy impact of locally controlled NML circuits. J. Emerg. Technol. Comput. Syst. 7, 2:1–2:24 (2011)
Zhao, H., Lyle, A., Zhang, Y., Amiri, P., Rowlands, G., Zeng, Z., Katine, J., Jiang, H., Galatsis, K., Wang, K., et al.: Low writing energy and sub nanosecond spin torque transfer switching of in-plane magnetic tunnel junction for spin torque transfer random access memory. J. Appl. Phys. 109(7), 07C720–07C720-3 (2011)
Das, J., Alam, S., Bhanja, S.: Nano magnetic STT-logic partitioning for optimum performance. IEEE Trans. Very Large Scale Integr. VLSI Syst. 22, 90–98 (2014)
Das, J., Alam, S., Bhanja, S.: A novel design concept for high density hybrid cmos-nanomagnetic circuits. In: 2012 12th IEEE Conference on Nanotechnology (IEEE-NANO), pp. 1–6 (2012)
Acknowledgement
This work is partially supported by NSF Career Award CCF (0639624), NSF EMT/Nano CCF (0824838), NSF CRI (0551621) and USF Presidential Doctoral Fellowship.
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Das, J., Alam, S.M., Bhanja, S. (2014). STT-Based Non-Volatile Logic-in-Memory Framework. In: Anderson, N., Bhanja, S. (eds) Field-Coupled Nanocomputing. Lecture Notes in Computer Science(), vol 8280. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-43722-3_8
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