This chapter describes a fast real time gray scale based feature point detector and its hardware architecture for FPGA based realization. The implementation is based on a new efficient technique which is fusion of both affine transformation invariance and robustness to noise. The novelty of the proposed approach lies in its highly accurate localization and realization only in terms of addition, subtraction and logic operations. The algorithm is designed to keep the high throughput requirements of today's feature point detectors and applications in Silicon. The proposed implementation is highly modular with custom scalability to fit devices like FPGAs etc, with different resource capacity. The implementation can be ported to any real time vision processing systems where power and speed are of utmost concern.
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Nain, N., Kumar, R., Bhadviya, B. (2009). A Gray Level Feature Detector and Its Hardware Architecture. In: Ao, SI., Gelman, L. (eds) Advances in Electrical Engineering and Computational Science. Lecture Notes in Electrical Engineering, vol 39. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-2311-7_12
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DOI: https://doi.org/10.1007/978-90-481-2311-7_12
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