Algorithm Design for Hardware-Based Computing Technologies

Abstract

This chapter first provides a brief discussion of the fundamental properties of both FPGA and ASIC devices, together with their relative merits, before analyzing the various design techniques and parameters – namely those relating to the clock frequency, silicon area and switching frequency – and the constraints and trade-offs that need to be made between them when trying to design a low-power solution to the regularized FHT for implementation with such technologies. The benefits of incorporating scalability, partitioned-memory processing and flexibility into the design of the proposed solution are considered as well as the design options available for silicon-based implementation when constrained by the limited availability of embedded resources. A discussion is finally provided relating to the results obtained in the chapter.