Abstract
As technology continues to evolve, communication is becoming the bottleneck of future systems as it significantly impacts overall performance and cost. The energy consumed in the communication of future many-core processors will be critical in achieving a scalable many-core system. In this chapter, we present energy-aware on-chip network architectures that attempt to achieve ideal on-chip network behavior by approaching the latency and energy consumed in the wires in transmitting data from source to destination. We present different techniques, including topology, flow control, and router microarchitecture, that attempt to achieve this ideal on-chip network. These approaches minimize the energy and latency overhead of intermediate routers as packets traverse the network. In addition to these approaches, we describe an alternative approach, i.e., bufferless on-chip networks, which minimize the amount of network buffers to reduce energy consumption.
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Notes
- 1.
The latency calculations were based on Intel TeraFlop [18] parameters (t r=1.25 ns, b=16 GB/s, L=320 bits) and an estimated value of wire delay for 65 nm (t w=250 ps/mm).
- 2.
Some amount of storage is still needed; for example, pipeline registers are still needed and, if the router microarchitecture requires multiple cycles, additional internal storage would be required.
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Kim, J. (2011). Energy-Aware On-Chip Networks. In: Kyung, CM., Yoo, S. (eds) Energy-Aware System Design. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1679-7_5
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DOI: https://doi.org/10.1007/978-94-007-1679-7_5
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