Abstract
Digital circuits necessarily include storage elements to ensure correct operation. The most common are the flip-flops (FFs). Although they are not very difficult to use, their operation must be understood and they must be characterized due to their timing metrics. They are not immune to failures, and one failure that FFs can present is the hold time violation, if they are not carefully designed. This chapter discusses FF operation and metrics, and hold time violations.
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References
BALSARA, P. T.; KO, U. High-Performance Energy-Efficient D-Flip-Flop Circuits. IEEE Transactions on VLSI Systems, New York, v. 8, p. 94–98, Feb. 2000.
DALLY, W.; POULTON, J. Digital Systems Engineering. Cambridge, UK: Cambridge University Press, 1998.
HARRIS, D.; SUTHERLAND, I.; SPROUL, B. Logical Effort: Designing Fast CMOS Circuits. San Francisco, CA: Morgan Kaufmann, 1999.
HODGES, D.; JACKSON, H. Analysis and Design of Digital Integrated Circuits. New York: McGraw Hill, 1988.
Marković, D. Analysis and Design of Low-Energy Clocked Storage Elements. 2000. Master Dissertation, Electrical Engineering and Computer Sciences – University of California at Berkeley.
RABAEY, J. M. Digital Integrated Circuits: A Design Perspective. Upper Saddle River, NJ: Prentice Hall, 1996.
STOJANOVIC, V. OKLOBDZIJA, V. G. Comparative Analysis of Máster-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems. IEEE Journal of Solid-State Circuits, New York, v. 34, p. 536–548, Apr. 1999.
SVENSSON, C.; YUAN, J. Latches and Flip-Flops for Low Power Systems. In: CHANDRAKASAN, A., BRODERSEN, R. (Ed.). Low Power CMOS Design. Piscataway, NJ: IEEE Press, 1998. p. 233–238.
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© 2014 Springer Science+Business Media Dordrecht
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Neuberger, G., Wirth, G., Reis, R. (2014). Flip-Flops and Hold Time Violations. In: Protecting Chips Against Hold Time Violations Due to Variability. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2427-3_3
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DOI: https://doi.org/10.1007/978-94-007-2427-3_3
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