Abstract
The common feature among the different 3D NAND solutions is constituted by very deep vertical (z direction) etching steps that define the Flash cells geometries simultaneously. Transistor geometries are formed by the deep trench through a multiple polysilicon/oxide stack. The most popular cells stacks are Vertical-Channel (VC) and Vertical-Gate (VG). In VC gate-all-around type, the channel is realized by etching a hole through the layers stack in one single step, and then forming the transistor structure with deposition of its ONO charge trapping layers, tunnel oxide and the polysilicon channel fill in the middle. The cell gates are constituted by the polysilicon horizontal layer surrounding the vertical channel forming a Gate-All-Around (GAA) structure. The string current flows in the cells in the vertical direction. In the VG-type the vertical etching is necessary to separate the strings in one direction and to separate the wordlines in the other direction. The current flows in horizontal direction and each layer must be connected to the top metal bitlines and source lines by a proper connecting structure. This chapter digs into the details of Vertical-Gate architectures.
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References
H. Tanaka et al., Bit cost scalable technology with punch and plug process for ultra high density flash memory, in VLSI Symposium Technical Digest (2007)
R. Katsumata, M. Kito et al., Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage device, in Symposium on VLSI Technology (2009)
K. Sakuna et al., Highly scalable horizontal channel 3-D NAND memory excellent in compatibility with conventional fabrication technology, in EDL, vol. 34Â (2013)
J. Jang, H.S. Kim et al., Vertical cell array using TCAT(terabit cell array transistor) technology for ultra high density NAND flash memory, in IEDM (2009)
J. Kim, A.J. Hong et al., Novel vertical-stacked-array-transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (solid state drive), in Symposium on VLSI Technology (2009)
K,T. Park, D.S. Byeon, A world’s first product of three-dimensional vertical NAND Flash memory and beyond, in NVMTS (2014)
K.T Park et al., Three-dimensional 128Â Gb MLC vertical NAND flash-memory with 24-WL stacked layers and 50Â MB/s high-speed programming, in ISCC (2014)
H.T. Lue, T.H. Hsu et al., A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device, in VLSI Symposia on Technology (2010)
H.T. Lue, T.H. Hsu et al., A novel double-density single gate vertical channel (SGVC) 3D NAND that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity, in IEDM (2015)
S.H. Chen, H.T. Lue et al., A highly scalable 8-layer vertical gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (minimal incremental layer cost) staircase contacts, in International Electron Device Meeting (IEDM), session 2-3 (2012)
S.J. Whang, K.J. Lee et al., A novel three-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell, in IEDM (2010)
E.S. Choi et al., A novel 3D cell array architecture for terra-bit NAND flash memory, in IMW (2011)
E.S. Choi, S.K. Park, Device considerations for high-density and highly reliable 3D NAND Flash cell in near future, in International Electron Device Meeting (IEDM), session 9-4 (2012)
K. Parat, C. Dennison, A floating gate based 3D NAND technology with CMOS under array, in IEDM 2015
J. Choi, K.S. Seol, 3D approaches for non-volatile memory, in VLSI (2011)
K.T. Park, J.M. Han et al., tree-dimensional 128Â Gb MLC vertical NAND flash memory with 24WL stacked layers and 50Â MB/s high speed programming, in ISSCC (2014)
Y. Fukuzumi, R. Katsumata, Optimal integration and characteristics of vertical array devices for ultra-high density, bit-cost scalable flash memory, in IEDM (2007)
W. Kim, S. Choi et al., Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage, in Symposium on VLSI Technology (2009)
C.H. Hung, H.T. Lue et al., A highly scalable vertical gate (VG) 3D NAND flash with robust program disturb immunity using a novel PN diode decoding structure, in VLSI Symposia on Technology, session 4B-1 (2011)
C.P. Chen, H.T. Lue et al., A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL), in VLSI Symposia on Technology (2012)
K.P. Chang, H.T. Lue et al., An efficient memory architecture for 3D vertical gate (3DVG) NAND flash using plural island-gate SSL decoding and study of its program inhibit characteristics, in International Memory Workshop (IMW) (2012)
T.H. Yeh, P.Y. Du, Increasing VG-type 3D NAND flash cell density by using ultrathin polysilicon channels, in IMW (2013)
H.-T. Lue, R. Lo, A novel double-trapping BE-SONOS charge-trapping NAND flash device to overcome the erase saturation without using curvature-induced field enhancement effect or high-K (HK)/metal gate (MG) materials, in IEEE IEDM (2014)
C.C. Hsieh, H.T. Lue et al., Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage, in VLSI Symposia on Technology, session 11-3 (2013)
W.C. Chen, H.T. Lue, Study of the programming sequence induced back-pattern effect in split-page 3D vertical-gate (VG) NAND flash, in VLSI-TSA (2014)
T.H. Yeh, C.J. Wu et al., A new string decoding scheme for enhancing array block efficiency of vertical gate type (VG-Type) 3-D NAND. EDL 36(4), 2 (2015)
H.T. Lue, Tutorial 3D NAND, in IMW (2014)
C.H. Hung, H.T. Lue et al., Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash, in International Electron Device Meeting (IEDM), session 10-1 (2012)
Y.-R. Chen, C.-J. Wu, Trapping-free string select transistors and ground select transistors for VG-type 3D NAND flash memory, in IMW (2014)
R. Micheloni et al., Inside NAND Flash Memories (Springer, Netherlands, 2010)
C.H. Hung, M.F. Chang et al., Layer-aware program and read schemes for 3D stackable Vertical-Gate BE-SONOS NAND flash against cross-layer process variations. IEEE JSSC 50(6) (2015)
A. Maconi, C.M. Compagnoni et al., A new erase saturation issue in cylindrical junction-less charge-trap memory arrays, in IEDM (2012)
Y.H. Hsiao, H.T. Lue, A critical examination of 3D stackable NAND flash memory architectures by simulation study of the scaling capability, in IMW (2010)
E.S. Choi, H.-S. Yoo, A novel 3D cell array architecture for terra-bit NAND flash memory, in IMW (2013)
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The author would like to thank Macronix International for the use of publications which have been cited in this chapter.
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Silvagni, A. (2016). 3D VG-Type NAND Flash Memories. In: Micheloni, R. (eds) 3D Flash Memories. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7512-0_7
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DOI: https://doi.org/10.1007/978-94-017-7512-0_7
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