Skip to main content
SpringerLink
Log in

Steep Slope Tunnel FET Simulation

  • Chapter
  • First Online:
3D TCAD Simulation for CMOS Nanoeletronic Devices

  • 5201 Accesses

Abstract

The simplest way for increasing the transistor density in the wafer is to reduce the feature size of transistor.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 79.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 99.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 129.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329 (2011)

    Article  Google Scholar 

  2. K. Jeon, W.Y. Loh, P. Patel, C.Y. Kang, J. Oh, A. Bowonder, C. Park, C.S. Park, C. Smith, P. Majhi, H.H. Tseng, R. Jammy, T.J. King Liu, C. Hu, Si tunnel transistors with a novel silicided source and 46 mV/dec swing. VLSI Tech. Symp. 121 (2010)

    Google Scholar 

  3. S. Richter, C. Sandow, A. Nichau, S. Trellenkamp, M. Schmidt, R. Luptak, K.K. Bourdelle, Q.T. Zhao, S. Mantl, Ω-gated silicon and strained silicon nanowire array tunneling FETs. IEEE Electr. Dev. Lett. 33, 1535 (2012)

    Google Scholar 

  4. K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Dev. 54, 1725 (2007)

    Article  Google Scholar 

  5. K.T. Lam, D. Seah, S.K. Chin, S.B. Kumar, G. Samudra, Y.C. Yeo, G. Liang, A simulation study of graphene-nanoribbon tunneling FET with heterojunction channel. IEEE Electr. Dev. Lett. 31, 555 (2010)

    Article  Google Scholar 

  6. Q. Huang, Z. Zhan, R. Huang, X. Mao, L. Zhang, Y. Qiu, Y. Wang, Self-depleted T-gate Schottky barrier tunneling FET with low average subthreshold slope and high Ion/Ioff by gate configuration and barrier modulation. Tech. Digest of IEDM 13.2.1 (2011)

    Google Scholar 

  7. Y.R. Jhan, Y.C. Wu, M.F. Hung, Performance enhancement of nanowire tunnel field-effect transistor with asymmetry-gate based on different screening length. IEEE Electr. Dev. Lett. 34, 1482 (2013)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan

    Yung-Chun Wu & Yi-Ruei Jhan

Authors
  1. Yung-Chun Wu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yi-Ruei Jhan
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Yung-Chun Wu .

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Nature Singapore Pte Ltd.

About this chapter

Cite this chapter

Wu, YC., Jhan, YR. (2018). Steep Slope Tunnel FET Simulation. In: 3D TCAD Simulation for CMOS Nanoeletronic Devices. Springer, Singapore. https://doi.org/10.1007/978-981-10-3066-6_7

Download citation

  • DOI: https://doi.org/10.1007/978-981-10-3066-6_7

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-3065-9

  • Online ISBN: 978-981-10-3066-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation