Abstract
Sequential circuits like pulsed latches and semi-dynamic flip-flops are extensively used in state-of-the-art high performance microprocessors. In this paper, we proposed a novel approach of exploiting the metal gate workfunction to reduce the power consumption and area of the pulsed latches and semi-dynamic flip-flops made using FinFETs. Compared to the design using standard shorted gate FinFETs, the proposed pulsed latch reduces the dynamic and leakage power by 37% and 42% respectively. Similarly, the proposed semi-dynamic flip-flop shows a reduction of 24% and 32% respectively in dynamic and leakage power consumption compared to the standard design. The proposed circuits also show significant improvement in static noise margin and reduction in area.
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Soni, A., Umap, A., Mohapatra, N.R. (2017). Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETs . In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_23
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DOI: https://doi.org/10.1007/978-981-10-7470-7_23
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