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Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies

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VLSI Design and Test (VDAT 2017)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 711))

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Abstract

The impact of high energy particles in digital memory elements becomes important as technology scales down. The memory elements hold high density latches to store data and these latches are susceptible to disturbs due to particle strikes. The alpha particles, neutrons from cosmic rays may cause Single Event Upset (SEU) in memory cells. In this paper, we propose a method to estimate and compare SER robustness of different layout topologies of SRAM cell. We demonstrate that the radiation hardened layout topologies offer much better Soft Error Rate (SER) robustness compared to conventional layout of the 6-T SRAM cell in 28FDSOI and 40 nm technology. The analysis is done using ELDO simulator for a wide range of Linear Energy Transfer (LET) profiles of particle strikes.

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Correspondence to Anand Ilakal .

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© 2017 Springer Nature Singapore Pte Ltd.

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Ilakal, A., Grover, A. (2017). Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_41

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  • DOI: https://doi.org/10.1007/978-981-10-7470-7_41

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-7469-1

  • Online ISBN: 978-981-10-7470-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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