Abstract
Through-silicon via (TSV)-interposer is very expensive [1,2,3,4,5,6,7,8,9,10]. Silicon bridges are one form of silicon substrates to support heterogeneous integrations. Basically, a bridge is a piece of dummy silicon with RDLs (redistribution-layers) and contact pads, but without TSVs (through-silicon vias), i.e., a TSV-less interposer. Usually, the RDLs and contact pads are fabricated on a dummy silicon wafer and then diced into individual bridges. In this chapter, the fabrication of Intel’s EMIB (embedded multi-die interconnect bridge) [11,12,13] will be mentioned. Also, imec’s bridges [14] for the communications of heterogeneous integrations will be briefly discussed. Finally, ITRI’s TSH (through-silicon hole) interposer (bridge) [15,16,17,18] will be presented.
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References
Hou, S., W. Chen, C. Hu, C. Chiu, K. Ting, T. Lin, W. Wei, W. Chiou, V. Lin, V. Chang, C. Wang, C. Wu, and D. Yu, “Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology,” IEEE Transactions on Electron Devices, October 2017, pp. 4071–4077.
Lee, J., C. Lee, C. Kim, and S. Kalchuri, “Micro Bump System for 2nd Generation Silicon Interposer with GPU and High Bandwidth Memory (HBM) Concurrent Integration,” Proceedings of IEEE/ECTC, May 2018, pp. 607–612.
Xie, J., H. Shi, Y. Li, Z. Li, A. Rahman, K. Chandrasekar, et al., “Enabling the 2.5D integration,” Proceedings of IMAPS International Symposium on Microelectronics, October 2012, pp. 254–267.
Shao, S., Y. Niu, J. Wang, R. Liu, S. Park, H. Lee, G. Refai-Ahmed, and L. Yip, “Comprehensive Study on 2.5D Package Design for Board-Level Reliability in Thermal Cycling and Power Cycling,” Proceedings of IEEE/ECTC, May 2018, pp. 1662–1669.
McCann, S., H. Lee, G. Refai-Ahmed, T. Lee, and S. Ramalingam, “Warpage and Reliability Challenges for Stacked Silicon Interconnect Technology in Large Packages,” Proceedings of IEEE/ECTC, May 2018, pp. 2339–2344.
Lau, J. H., 3D IC Integration and Packaging, McGraw-Hill, New York, 2016.
Lau, J. H., Through-Silicon Via (TSV) for 3D Integration, McGraw-Hill, New York, 2013.
Lau, J. H., Reliability of RoHS compliant 2D & 3D IC Interconnects, McGraw-Hill, New York, 2011.
Lau, J. H., C. K. Lee, C. S. Premachandran, and Yu Aibin, Advanced MEMS Packaging, McGraw-Hill, New York, 2010.
Chai, T. C., X. Zhang, J. H. Lau, C. S. Selvanayagam, D. Pinjala, et al., “Development of Large Die Fine-Pitch Cu/low-k FCBGA Package with through Silicon via (TSV) Interposer,” IEEE Transactions on CPMT, Vol. 1, No. 5, May 2011, pp. 660–672.
Chiu, C., Z. Qian, and M. Manusharow, “Bridge Interconnect with Air Gap in Package Assembly,” US Patent No. 8,872,349, 2014.
Mahajan, R., R. Sankman, N. Patel, D. Kim, K. Aygun, Z. Qian, et al., “Embedded multi-die interconnect bridge (EMIB)—a high-density, high-bandwidth packaging interconnect,” IEEE/ECTC Proceedings, May 2016, pp. 557–565.
Podpod, A., J. Slabbekoorn, A. Phommahaxay, F. Duval, A. Salahouedlhadj, M. Gonzalez, K. Rebibis, R.A. Miller, G. Beyer, and E. Beyne, “A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-μm Pitch,” IEEE/ECTC Proceedings, May 2018, pp. 370–378.
Wu, S., J. H. Lau,, H. Chien, R. Tain, M. Dai, and Y. Chao, “Chip Stacking Structure and Fabricating Method of the Chip Stacking Structure,” US Patent No.: 8,519,524, Date of Patent: August 27, 2013.
Wu, S., J. H. Lau, H. Chien, J. Hung, M. Dai, Y. Chao, R. Tain, et al., “Ultra Low-Cost Through-Silicon Holes (TSHs) Interposers for 3D IC Integration SiPs,” IEEE ECTC Proceedings, San Diego, CA, May 2012, pp. 1618–1624.
Lau, J. H., C. Lee, C. Zhan, S. Wu, Y. Chao, M. Dai, R. Tain, H. Chien, C. Chien, R. Cheng, Y. Huang, Y. Lee, Z. Hsiao, W. Tsai, P. Chang, H. Fu, Y. Cheng, L. Liao, W. Lo, and M. Kao, “Low-Cost TSH (Through-Silicon Hole) Interposers for 3D IC Integration,” Proceedings of IEEE/ECTC, Orlando, FL, May 2014, pp. 290–296.
Lau, J. H., C. Lee, C. Zhan, S. Wu, Y. Chao, M. Dai, R. Tain, et al. 2014. Through-Silicon Hole Interposers for 3D IC Integration. IEEE Transactions on CPMT 4 (9): 1407–1418.
Lau, J. H., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, et al. 2014. Redistribution Layers (RDLs) for 2.5D/3D IC Integration, IMAPS Transactions, Journal of Microelectronic Packaging, 11 (1), First Quarter 2014, pp. 16–24.
JESD22–B111, Board Level Drop Test Method of Components for Handheld Electronic Products, JEDEC Standard, July 2003.
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Lau, J.H. (2019). Heterogeneous Integrations on Silicon Substrates (Bridges). In: Heterogeneous Integrations. Springer, Singapore. https://doi.org/10.1007/978-981-13-7224-7_4
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DOI: https://doi.org/10.1007/978-981-13-7224-7_4
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