Abstract
This chapter gives an introduction to the concepts of a computing paradigm called invasive computing, which has been introduced to tackle different problems that arise when designing and programming complex multi-core architectures comprising of hundreds to thousands of cores as well as hardware accelerators on a single chip (e.g., overheating, reliability, and power issues as well as resource contention). The basic principles of invasive computing as well as the realization of these concepts in hardware and software are explained. This chapter outlines the challenges in designing and programming future many-core architectures as well as the concepts of invasive computing on all layers from the hardware, over the runtime system to the language implementation. These concepts are introduced by the help of illustrations, graphs, and code snippets. Furthermore, a detailed introduction of the concepts, language constructs, and runtime implementation of the parallel programming language X10 is presented, which acts as the fundamental basis for realizing the ideas of invasive computing (InvadeX10) as well as for implementing the full-system simulator InvadeSIM and the actor-oriented programming library ActorX10. By the help of descriptive graphics, detailed descriptions, and various code examples, the partitioned global address space programming model, essential language features of X10 including extensions to the sequential core and the language constructs for concurrency, synchronization, and distribution as well as the X10 runtime system are explained, which helps the reader to understand modern concepts of parallel and distributed programming languages.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
Invasive Computing is the title as well as the research focus of the Transregional Collaborative Research Center 89 (http://www.invasic.de).
- 2.
In the following, we use application and parallel application program synonymously.
- 3.
This conception goes back to the notion of a servlet, which is a (Java) application program snippet targeted for execution within a web server.
- 4.
The basis for the following syntax and semantics descriptions is the X10 version 2.3.1, which has been also used for all implementations in this book.
- 5.
Central control-flow structures of an imperative programming language are if-then-else statements, for loops, while loops, switch statements, try-catch blocks, and throw.
- 6.
A thread is considered as kernel-level thread, which is the smallest scheduling unit in an operating system. It is part of an operating system process and might concurrently co-exist beside many other threads in a process. All threads of a process share the same address space and may communicate via shared memory. Kernel-level threads are created and managed by the operating system kernel, which might be very expensive for thousands of threads considering the number of required system calls, context switches, and kernel-level resources.
- 7.
All X10 implementations and modifications presented in this book are based on the C++ back end.
References
J. Teich, Invasive algorithms and architectures. It Inf. Technol. 50(5), 300–310 (2008). ISSN: 1611-2776. https://doi.org/10.1524/itit.2008.0499
J. Teich et al., Invasive computing: an overview, in Multiprocessor System-on-Chip: Hardware Design and Tool Integration, ed. by M. Hübner, J. Becker. (Springer, Heidelberg, 2011), pp. 241–268 (Chap. 11). ISBN: 978-1-4419-6459-5. https://doi.org/10.1007/978-1-4419-6460-1
J. Teich et al., Invasive computing-concepts and overheads, in Proceeding of the Forum on Specification and Design Languages (FDL), Vienna, Austria, 18–20 Sept 2012 (IEEE, 2012), pp. 217–224. ISBN: 978-1-4673-1240-0
F. Hannig et al., Resource-aware programming and simulation of MPSoC architectures through extension of X10, in Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems (SCOPES), St. Goar, Germany, 27–28 June 2011 (ACM, 2011), pp. 48–55. ISBN: 978-1-4503-0763-5. https://doi.org/10.1145/1988932.1988941
A. Tanase et al., Exploitation of quality/throughput tradeoffs in image processing through invasive computing, in Proceedings of the International Conference on Parallel Computing (ParCo), Munich, Germany, 10–13 Sept 2013 (IOS Press, 2013), pp. 53–62. https://doi.org/10.3233/978-1-61499-381-0-53
S. Roloff et al., Invasive computing for predictable stream processing: a simulation-based case study, in Proceedings of the 13th IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), Amsterdam, The Netherlands, 8–9 Oct 2015 (IEEE, 2015). ISBN: 978-1-4673- 8164-2. https://doi.org/10.1109/ESTIMedia.2015.7351761
S. Wildermann et al., Invasive computing for timing-predictable stream processing on MPSoCs. It Inf. Technol. (IT) 58(6), 267–280 (2016). ISSN: 1611-2776. https://doi.org/10.1515/itit-2016-0021
J. Turek, J.L. Wolf, P.S. Yu, Approximate algorithms scheduling parallelizable tasks, in Proceedings of the 4th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA), San Diego, CA, USA, June 29–July 1 1992 (ACM, 1992), pp. 323–332. ISBN: 0-89791-483-X. https://doi.org/10.1145/140901.141909
D.G. Feitelson et al., Theory and practice in parallel job scheduling, in Job Scheduling Strategies for Parallel Processing (JSSPP). ed. by D.G. Feitelson, L. Rudolph. (Springer, Heidelberg, 1997), pp. 1–34. ISBN: 978-3-540-69599-8. https://doi.org/10.1007/3-540-63574-2_14
S. Kobbe et al., DistRM: distributed resource management for onchip many-core systems, in Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Taipei, Taiwan, 9–14 Oct 2011 (IEEE, 2011), pp. 119–128. ISBN: 978-1-4503-0715-4. https://doi.org/10.1145/2039370.2039392
S. Wildermann, T. Ziermann, J. Teich, Game-theoretic analysis of decentralized core allocation schemes on many-core systems, in Proceedings of the Conference on Design, Automation and Test in Europe (DATE), Grenoble, France, 18–22 Mar 2013 (EDA Consortium, 2013), pp. 1498–1503. ISBN: 978-1-4503-2153-2
A. Tanase et al., On-demand fault-tolerant loop processing on massively parallel processor arrays, in Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Toronto, Canada, 27–29 July 2015 (IEEE, 2015), pp. 194–201. ISBN: 978-1-4799-1925-3. https://doi.org/10.1109/ASAP.2015.7245734
V. Lari et al., Providing fault tolerance through invasive computing. It Inf. Technol. 58(6), 309–328 (2016). ISSN: 1611-2776. https://doi.org/10.1515/itit-2016-0022
V. Lari et al., Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 18(1), 2:1–2:25 (2013). ISSN: 1084-4309. https://doi.org/10.1145/2390191.2390193
H. Khdr et al., Power density-aware resource management for heterogeneous tiled multicores. IEEE Trans. Comput. (TC) 66(3), pp. 488–501 (2017). ISSN: 0018-9340. https://doi.org/10.1109/TC.2016.2595560
H.-J. Bungartz et al., Invasive computing in HPC with X10, in Proceedings of the 3rd ACM SIGPLAN X10 Workshop (X10), Seattle, WA, USA, 20 June 2013 (ACM, 2013), pp. 12–19. ISBN: 978-1-4503-2157-0. https://doi.org/10.1145/2481268.2481274
M. Bader, H.-J. Bungartz, M. Schreiber, Invasive computing on high performance shared memory systems, in Facing the Multicore-Challenge III: Aspects of New Paradigms and Technologies in Parallel Computing, ed. by R. Keller, D. Kramer, J.-P. Weiss. (Springer, Heidelberg, 2013), pp. 1–12. ISBN: 978-3-642-35893-7. https://doi.org/10.1007/978-3-642-35893-7_1
J. Heisswolf et al., The invasive network on chip-a multi-objective many-core communication infrastructure, in Workshop Proceedings of the 27th International Conference on Architecture of Computing Systems (ARCS), Lübeck, Germany, 25–28 Feb 2014 (VDE Verlag, 2014), pp. 1–8. ISBN: 978-3-8007-3579-2
J. Henkel et al., Invasive manycore architectures, in Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, NSW, Australia, Jan 30–Feb 2 2012 (IEEE, 2012), pp. 193–200. ISBN: 978-1-4673-0770-3. https://doi.org/10.1109/ASPDAC.2012.6164943
J. Henkel et al., i-Core: a run-time adaptive processor for embedded multi-core systems, in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, USA, 18–21 July 2011 (2011), pp. 1–8
F. Hannig et al., Invasive tightly-coupled processor arrays: a domain-specific architecture/compiler co-design approach. ACM Trans. Embed. Comput. Syst. (TECS) 13(4), pp. 133:1–133:29 (2014). ISSN: 1539-9087. https://doi.org/10.1145/2584660
J. Heisswolf, R. König, J. Becker, A scalable NoC router design providing QoS support using weighted round robin scheduling, in IEEE 10th International Symposium on Parallel and Distributed Processing with Applications (ISPA), Leganes, Spain, 10–13 July 2012 (IEEE, 2012), pp. 625–632. ISBN: 978-1-4673-1631-6. https://doi.org/10.1109/ISPA.2012.93
L. Dagum, R. Menon, OpenMP: An industry standard API for shared-memory programming. IEEE Comput. Sci. Eng. 5(1), 46–55 (1998). ISSN: 1070-9924. https://doi.org/10.1109/99.660313
M. Gerndt et al., Invasive computing with iOMP, in Proceeding of the Forum on Specification and Design Languages (FDL), Vienna, Austria, 18–20 Sept 2012 (IEEE, 2012), pp. 225–231. ISBN: 978-1-4673-1240-0
Message Passing Interface Forum. MPI: a message-passing interface standard. Technical Report (1994)
I.A. Comprés, M. Riepen, M. Konow, M. Gerndt, Invasive MPI on intel’s single-chip cloud computer, in Proceedings of the 25th International Conference on Architecture of Computing Systems (ARCS), Prague, Czech Republic. ed. by A. Herkersdorf, K. Römer, U. Brinkschulte. (Springer, Heidelberg, Feb 28–Mar 2 2012), pp. 74–85. ISBN: 978-3-642-28292-8. https://doi.org/10.1007/978-3-642-28293-5_7
I.A. Comprés et al., Infrastructure and API extensions for elastic execution of MPI applications, in Proceedings of the 23rd European MPI Users’ Group Meeting (EuroMPI), Edinburgh, United Kingdom, 25–28 Sept 2016 (ACM, 2016), pp. 82–97. ISBN: 978-1-4503-4234-6. https://doi.org/10.1145/2966884.2966917
P. Charles et al., X10: an object-oriented approach to non-uniform cluster computing, in Proceedings of the 20th Annual ACM SIGPLAN Conference on Object-oriented Programming, Systems, Languages, and Applications (OOPSLA), San Diego, CA, USA, 16–20 Oct 2005 (ACM, 2005), pp. 519–538. ISBN: 1-59593-031-0. https://doi.org/10.1145/1094811.1094852
B. Oechslein et al., OctoPOS: a parallel operating system for invasive computing, in Proceedings of the International Workshop on Systems for Future Multi-Core Architectures (SFMA), Salzburg, Austria, 10 Apr 2011 (2011), pp. 9–14
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this chapter
Cite this chapter
Roloff, S., Hannig, F., Teich, J. (2019). Fundamentals. In: Modeling and Simulation of Invasive Applications and Architectures. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-13-8387-8_2
Download citation
DOI: https://doi.org/10.1007/978-981-13-8387-8_2
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-8386-1
Online ISBN: 978-981-13-8387-8
eBook Packages: EngineeringEngineering (R0)