Abstract
A parallel accessing schedule of multi-channel Nand Flash for signal processing system on board is proposed, which obtains high-performance in throughput rate with the combine of intra-channel pipeline and inter-channel interleaving. The massive data storage efficiency assessment model is established to calculate the bandwidth formula of the proposed method. The parameters which affect the parallel access rate of multi-channel Nand Flash memory are analyzed. The proposed architecture is implemented in a Virtex II FPGA, and is applied in the signal processing system on board. With 8-stage intra-channel interleaving and 4-stage inter-channel pipeline, the throughput of Nand Flash storage system can reach about 560 MBps for store and about 220 MBps for playback, which is more efficient compared with previous literatures. The results of the experiments verify the advantages and feasibility of the proposed method.
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Li, X., Yu, JY., Li, K., Chen, MS., Ma, JY. (2020). A High-Speed Parallel Accessing Scheduler of Space-Borne Nand Flash Storage System. In: Liang, Q., Wang, W., Liu, X., Na, Z., Jia, M., Zhang, B. (eds) Communications, Signal Processing, and Systems. CSPS 2019. Lecture Notes in Electrical Engineering, vol 571. Springer, Singapore. https://doi.org/10.1007/978-981-13-9409-6_123
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DOI: https://doi.org/10.1007/978-981-13-9409-6_123
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