Abstract
Real-time image processing in the field of computer vision is not only a challenging task, but requires several embedded computing considerations. In the present era, FPGA-based reconfigurable architecture is widely used for its parallel computing compatibility and fast hardware prototyping. In this paper, a 2D convolution operation is applied to the complete image by splitting it into vertical blocks on which row buffering is applied separately without any substantial increase in the buffer storage area. The proposed technique reduces the execution time with each parallelism stage and utilizes lesser hardware resource as compared to other partitioning schemes. As compared to several existing parallelizing scheme for data processing through FPGA, vertical splitting has been found to work promisingly. Additionally, a table indicating the optimum parallelism stages achievable with given timing constraints, memory bandwidth and, available resources is provided.
Sonam Rani and Bipin Koli contributed to this worked in the past during their tenure with CSIR—Central Scientific Instruments Organisation, Chandigarh.
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References
Hau N, Asari V (2009) Neighborhood dependent approach for low power 2D convolution in video processing applications. In: 2009 4th IEEE conference on industrial electronics and applications, 2009, ICIEA 2009, pp 656–661
Benedetti A, Prati A, Scarabottolo N (1998) Image convolution on FPGAs: the implementation of a multi-FPGA FIFO structure. In: 1998 Proceedings. 24th Euromicro conference, 1998, pp 123–130
Zhang H, Xia M, Hu G (2007) A multiwindow partial buffering scheme for FPGA-based 2-D convolvers. IEEE Trans Circuits Syst II: Express Briefs 54:200–204
Cao TP, Elton D, Deng G (2012) Fast buffering for FPGA implementation of vision-based object recognition systems. J Real-Time Image Process 7:173–183
Bosi B, Bois G, Savaria Y (1999) Reconfigurable pipelined 2-D convolvers for fast digital signal processing. IEEE Trans Very Large Scale Integr (VLSI) Syst 7:299–308
Javier Toledo-Moreo F, Javier Martínez-Alvarez J, Garrigós-Guerrero J, Manuel Ferrández-Vicente J (2012) FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size. J Syst Archit 58:277–285
Reichenbach M, Schmidt M, Fey D (2011) Analytical model for the optimization of self-organizing image processing systems utilizing cellular automata. In: 2011 14th IEEE international symposium on object/component/service-oriented real-time distributed computing workshops (ISORCW), 2011, pp 162–171
Johnston C, Gribbon K, Bailey D (2004) Implementing image processing algorithms on FPGAs. In: 2004 proceedings of the eleventh electronics New Zealand conference, ENZCon’04, pp 118–123
Yu H, Leeser M (2006) Automatic sliding window operation optimization for FPGA-based. In: 2006 14th annual IEEE symposium on field-programmable custom computing machines, 2006, FCCM’06, pp 76–88
Tessier R, Giza H (2000) Balancing logic utilization and area efficiency in FPGAs. In: Field-programmable logic and applications: the roadmap to reconfigurable computing. Springer, pp 535–544
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Poddar, S., Rani, S., Koli, B., Kumar, V. (2020). Area-Efficient Splitting Mechanism for 2D Convolution on FPGA. In: Sharma, H., Pundir, A., Yadav, N., Sharma, A., Das, S. (eds) Recent Trends in Communication and Intelligent Systems. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-15-0426-6_18
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DOI: https://doi.org/10.1007/978-981-15-0426-6_18
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