Abstract
In modern electronics, the continuous growth of wearable and portable devices like mobile phones, laptops and smart watches demands low-power consumption. Since flip-flop is a basic storage element of any device, flip-flop designing with low-power consumption is a very critical issue. In this paper, the design of double-edge-triggered (DET) flip-flop belonging to C-element using LECTOR technique is presented. As technology is scaling down continuously so leakage power is an important parameter on which circuit performance mainly depends, in this paper an improvement has been done by introducing effective arrangement of extra transistors in the conventional design. The conventional design and modified circuit are implemented at 45 nm CMOS technology using cadence virtuoso tool at different supply voltage varying from 0.7 to 1.1 V, and reduction in power consumption and improvement in the power delay product (PDP) is achieved as compared with the conventional design.
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References
Strollo, A.G.M., Napoli, E., Cimino, C.: Analysis of power dissipation in double edge-triggered flip-flops. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 8(5), 624–629 (2000)
Lapshev, S., Hasan, S.M.R.: New low glitch and low power DET flip-flops using multiple C-elements. IEEE Trans. Circuits Syst. I Regul. Paper. 63(10), 1673–1681 (2016)
Rohila, R., Vashishath, M.: CMOS LECTOR technique: a technique for leakage reduction in domino circuits. Int. J. Sci. Res. Dev. 3(03), 2279–2281 (2015)
Tschanz, J., Narendra, S., Zhanping, C., Borkar, S., Sachdev, M., De, V.: Comparative delay and energy of single edge-triggered and dual edge triggered pulsed flip-flops for high-performance microprocessors. In: International Symposium on Low Power Electronics and Design. pp. 147–152 (2001)
Muller, D. E.: Theory of asynchronous circuits. Internal Report no. 66, Digital Computer Lab University. Illinois at Urbana-Champaign (1955)
Devarapalli, S.V., Zarkesh-Ha, P., Suddarth, S.C.: A robust and low power dual data rate (DDR) flip-flop using C-elements. In: 11th International Symposium on Quality Electronic Design (ISQED). pp. 147–150 (2010)
Gago, A., Escano, R., Hidalgo, J.A.: Reduced implementation of D-type DET flip-flops. IEEE J. Solid-State Circuits 28(3), 400–402 (1993)
Bonetti, A., Teman, A., Burg, A.: An overlap-contention free true single-phase clock dual-edge-triggered flip-flop. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1850–1853 (2015)
Alioto, M., Consoli, E., Palumbo, G.: Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part I—Methodology and design strategies. IEEE Trans. Very Large Scale Integr. (VLSI) System. 19(5), 725–736 (2011)
Shams, M., Ebergen, J.C., Elmasry, M.I.: Modeling and comparing CMOS implementations of the C-element. IEEE Trans. Very Large Scale Integr. Syst. (VLSI) 6(4), 563–567 (1998)
Alioto, M., Consoli, E., Palumbo, G.: Analysis and comparison of variations in double edge triggered flip-flops. In: 5th European Workshop CMOS Variability (VARI), Palma de Mallorca, Spain, pp. 1–6 (2014)
Ji-ren, Y., Karlsson, I., Svensson, C.: A true single-phase-clock dynamic CMOS circuit technique. IEEE J. Solid-State Circuits 22, 899–901 (1987)
Svensson, C., Alvandpour, A.: Low power and low voltage CMOS digital circuit techniques. In: International symposium on low power electronics and design. pp. 7–10 (1998)
Renshaw, D., Lau, C.H.: Race-free clocking of CMOS pipelines using a single global clock. IEEE J. Solid-State Circuits 25, 766–769 (1990)
Stojanovic, V., Oklobdzija, V.G.: Comparative analysis of master slave latches and flip flops for high-performance and low-power systems. IEEE J. Solid-State Circuits 34(4), 536–548 (1999)
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Vaithiyanathan, D., Gupta, V., Kumar, S., Mishra, A.K., Britto Pari, J. (2020). Performance Analysis of Implicit Pulsed and Low-Glitch Power-Efficient Double-Edge-Triggered Flip-Flops Using C-Elements. In: Bindhu, V., Chen, J., Tavares, J. (eds) International Conference on Communication, Computing and Electronics Systems. Lecture Notes in Electrical Engineering, vol 637. Springer, Singapore. https://doi.org/10.1007/978-981-15-2612-1_25
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DOI: https://doi.org/10.1007/978-981-15-2612-1_25
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